Electronic digital logic circuitry – Tri-state – With field-effect transistor
Reexamination Certificate
1999-03-08
2001-05-01
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Tri-state
With field-effect transistor
C326S086000, C326S027000
Reexamination Certificate
active
06225824
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit devices, and more particularly to output buffer circuits for use in such devices.
BACKGROUND OF THE INVENTION
While various improvements in design approaches and manufacturing methods have led to increases in the speed at which data is processed within an integrated circuit, an important part of an integrated circuit's function continues to be how internal data signals are translated into output data signals for use by other devices. The propagation of data signals within an integrated circuit occurs on conductive lines of relatively small dimensions. Thus, the electrical loads presented by the internal conductive lines can be driven with relatively small transistors that draw small amounts of current. This is in contrast to the propagation of signals external to the integrated circuit device. In order to transmit data signals externally, an integrated circuit must drive a much larger capacitive and inductive load. The external load typically includes a bond wire that carries the electrical signal from the integrated circuit to a conductive lead frame. The lead frame provides the conductive leads (or pins) of the integrated circuit package. When the integrated circuit is use, the package pin will be electrically connected to other lines in an electronic system (e.g., soldered to a conductive line on a printed circuit board).
In order to ensure that the relatively large external loads are driven rapidly between various voltage levels, an integrated circuit typically includes an output buffer circuit for each output signal. Output buffer circuits include large semiconductor circuit elements that are capable of providing (“sourcing” or “sinking”) the relatively large amounts of current required to rapidly charge and discharge the external loads, and thereby generate an output signal.
An example of a prior art output buffer circuit is set forth in a schematic diagram in FIG.
1
. The output buffer circuit is designated by the general reference character
100
, and is shown to include an input latch
102
, a first pre-drive circuit
104
, a second pre-drive circuit
106
and an output driver circuit
108
. The input latch
102
includes two cross-coupled inverters I
100
and I
102
. The input latch
102
receives an input data signal (DATA), and latches the value to provide an inverse data signal (DATA_) to the first and second pre-drive circuits (
104
and
106
).
The first pre-drive circuit
104
receives the DATA
—
signal and an output enable signal (OE_), and in response to these signals, drives a first pre-drive node
110
between a high pre-drive potential and a low pre-drive potential. When the OE_ signal is high, the first pre-drive circuit
104
is disabled, and the first pre-drive node
110
is driven to a disable (high) potential. When the OE_ signal is low, the first pre-drive circuit
104
is enabled, and the first pre-drive node
110
voltage will follow from the DATA signal value. When the DATA_ signal is high, first pre-drive node
110
will be driven high. When the DATA_ signal is low, the first pre-drive node
110
will be driven low. The first pre-drive circuit
104
includes a two-input NOR gate G
100
that receives the OE
—
signal and the DATA_ signal as inputs. The output of gate G
100
is provided as an input to an inverter I
104
. The output of inverter I
104
drives the first pre-drive node
110
.
The second pre-drive circuit
106
receives the DATA_ signal and a second output enable signal OE. The signal OE is the inverse of the OE_ signal. In response to the DATA
—
and OE signal, the second pre-drive circuit
106
drives a second pre-drive node
112
between a enabling (high) pre-drive potential and a disabling (low) pre-drive potential. In a similar fashion to the first pre-drive circuit
104
, when the OE signal is low, the second pre-drive circuit
106
is disabled, and the second pre-drive node
112
is driven low. When the OE signal is high, the second pre-drive circuit
106
is enabled, and the second pre-drive node
112
voltage will follow the DATA_ signal value. The second pre-drive circuit
106
includes a two-input NAND gate G
102
that receives the OE signal and the DATA_ signal as inputs. The output of gate G
102
is provided as an input to an inverter I
106
. The output of inverter I
106
drives the second pre-drive node
112
.
The output driver circuit
108
drives an output node
114
to either a high supply voltage (VDD) or a low supply voltage (VSS) depending upon the potential at the first pre-drive node
110
and second pre-drive node
112
. The output driver circuit
108
includes p-channel metal-oxide-semiconductor (MOS) transistor P
100
having a source-drain path connected between the VDD voltage and the output node
114
. The gate of transistor P
100
is coupled to the first pre-drive node
110
. In a similar fashion, an n-channel MOS transistor N
100
has a source-drain path connected between the output node
114
and the VSS voltage. The gate of transistor N
100
is driven by the second pre-drive node
112
. The output node
114
provides a data output signal DATA_OUT.
The operation of the prior art output buffer circuit
100
is best understood with reference to
FIG. 2
in conjunction with FIG.
1
.
FIG. 2
is a timing diagram illustrating the OE signal, the DATA signal, and the DATA_OUT signal. In addition, the response of the first pre-drive node
110
and the second pre-drive node
112
are also set forth as waveforms “
110
” and “
112
” respectively.
Referring now to
FIG. 2
in conjunction with
FIG. 1
, at time t
0
the OE signal is low (and the OE
—
signal is high), disabling the output driver circuit
100
. The first pre-drive circuit
104
drives the first pre-drive node
110
high, turning off transistor P
100
. In the same fashion, the second pre-drive circuit
106
drives the second pre-drive node
112
low, turning off transistor N
100
.
At time t
1
, the OE signal transitions high (forcing OE_ low), and thereby enabling the output buffer circuit
100
. The high DATA signal propagates through the input latch
102
driving the DATA_ signal low. With the OE_ and DATA_ signals low, the output of gate G
100
is driven high. Inverter I
104
drives the first pre-drive node
110
low, turning on transistor P
100
. In this manner, the DATA_OUT signal is driven high to the VDD voltage. At the same time, the low DATA
—
signal and high OE signal are received by the second pre-drive circuit
106
. The output of gate G
102
remains high, and inverter I
106
maintains the second pre-drive node
112
low, keeping transistor N
100
off.
At time t
2
, with the OE signal still high, the DATA signal makes a first transition from high to low. The input latch
102
drives the DATA_ signal high. The high DATA_ signal results in the output of gate G
100
going low, and inverter I
104
drives the first pre-drive node
110
high. Transistor P
100
is turned off, isolating the output node
114
from the VDD voltage. At the same time, with the OE and DATA
—
signals high, the output of gate G
102
is driven low, and inverter I
106
drive the second pre-drive node
112
high, turning on transistor N
100
. The output node
114
is thus coupled to the VSS voltage, driving the DATA_OUT signal low.
At time t
3
, the DATA signal makes a second transition from low to high. The input latch
102
drives the DATA_ signal low. With a low DATA_ signal and a low OE_ signal, the output of gate G
100
is driven high once more, and inverter I
104
drives the first pre-drive node
110
low. Transistor P
100
is turned on, and the DATA_OUT signal is driven high once again. At the same time, as the DATA_ signal goes low at the input of gate G
102
, the output of gate G
102
is driven high, resulting in transistor N
100
being turned off.
At time t
4
, the OE signal returns low, placing the output buffer circuit
100
in the disabled state once again. As described for time t
0
, the first pre-drive node
110
is driven high, turning off transistor P
100
, an
Madhu R
Ray Abhijit
Brady III Wade James
Cho James H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
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