High speed on-chip signaling system and method

Details High speed on-chip signaling system and method High speed on-chip signaling system and method

2002-09-27

2004-04-27

Jeanglaude, Jean (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S116000, C326S031000, C327S108000

Reexamination Certificate

active

06727730

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a high speed signaling system and, more particularly, to circuitry used to forward high frequency signals across a line with minimal charge storage, power consumption and signal attenuation as caused by parasitic properties of the line, even though the line might extend a substantial distance across a semiconductor substrate. The system may include a transmitter and receiver that have low inductance couplings to the line or conductor to take advantage of the parasitic properties of the conductor when retrieving at the receiver a substantially lossless high-speed current signal.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Information within either a digital or analog system is typically conveyed as a signal along a conductor. In order to accurately discern the conveyed information, the signal must be placed upon a node at the proper time and having the proper magnitude as determined by factors such as the phase and magnitude of the transmitted signal and length and conductivity of the conductor. As the routing distance of the conductor increases, loading properties of the line can have a profound effect on the signal and whether the signal arrives at its destination at the proper time and amplitude.
To ensure accurate signaling, careful attention must be placed on the load and, particularly, the parasitic loading effects of a conductor to which a signal source and signal destination are coupled. Although undesired, any conductor that transports a signal has certain parasitic loading properties. Those properties can be modeled as resistor, capacitor, and inductor periodically placed along the conductor to impart an impedance on that conductor. The resistive and reactive components may cause a linear shift in phase as well as a change in amplitude on any transient signal forwarded on the conductor.
While an ideal conductor does not contain parasitics, such parasitics are nonetheless present to cause a destination circuit or subsystem connected thereto to receive a phase-shifted/attenuated signal that may cause the destination subsystem to receive the wrong information. For example, instead of receiving a targeted voltage at a specific time, an attenuated voltage might result at that time and the amount of attenuation might cause the destination subsystem to, for example, mistakenly read a logic low voltage value rather than a logic high voltage value.
The reactive and resistive components of impedance can oftentimes be modeled as a simple resistive-capacitive (“RC”) or resistive-inductive-capacitive (“RLC”) circuit. The RC or RLC components attribute an RC time constant or RLC time delay to any signal sent across the conductor. As the time constant increases, the amount of delay between a transient input signal to the conductor and a resultant, transient output signal will increase. The time constant and time delay affect the responsiveness at the receiving end, and the time constant is herein defined as the time difference between when an ideal step waveform would have reached a certain percentage of its eventual value at the receiver and when the real signal reaches that value, had an ideal step waveform been applied at the transmitting end of the conductor. An RLC time delay can be considered to be the time between when a transmitted waveform reaches a certain percentage of its eventual value at the transmit end and when the received waveform reaches that percentage of its eventual value. As the conductor increases in length, the amount of time delay will increase.
With the proliferation of integrated circuits, many conductors are by design placed partially across an integrated circuit from a source electronic subsystem to a destination electronic subsystem, also formed on the integrated circuit. According to well-known photolithography techniques, the conductor is a trace conductor patterned from a layer of metal or metal alloy. The metal trace conductor has certain plate and fringe capacitive effects and, due to the limited cross-section of the metal trace (as well as the metal conductive properties), the trace conductor also has a per-length resistive value.
Signals transmitted by electronic subsystems coupled to one end of a trace conductor experience the time delay and attenuation effects of the parasitic circuit, which will cause the input to the receiving electronic subsystem to misread the signal if the conductor is too long. Most designers recognize this problem and, in many instances, periodically place buffers that act as repeaters along the conductor. Each buffer requires power and, moreover, each buffer will introduce delay into the signal. Depending on the distances between buffers, the voltage swing at the source, and the clock frequency, significant charge can be stored on the parasitic capacitors in the interim between swings. The stored charge will cause relatively long conductors to consume significant power by virtue of charging and discharging the capacitance along the line, that manifests itself as current, and which performs no otherwise useful function and is therefore wasted. Total capacitance is proportional to the conductor length. Thus, charge being stored is proportional to the conductor length for a given voltage. Long conductors consume significant power partially due to parasitically stored charge and partially due to power consumption at each buffer. Undue delay coupled with unsatisfactory power consumption can cause significant problems for high-speed circuits.
It would be desirable to implement a new signaling system and method that avoids having to periodically buffer signals sent across an on-chip trace conductor, or having to use any of the other methods conventionally available and appropriate. As defined herein, “on-chip” means a conductor formed during photolithography upon a portion of a monolithic substrate. The improved signaling system should avoid the conventional methodology of using either voltage signaling or current signaling. In other words, the improved system need not use a voltage source for generating a signal onto a line and an electronic system at the destination that recognizes voltage levels, albeit attenuated and possibly delayed. The same can be said for current signaling, where current is driven onto the line and fluctuations in current are received at the destination. Instead, the desired system should be one that welcomes the effect of at least parasitic resistance by using a variable voltage driven onto the line and received as a variable current, measured as the variable voltage divided by the parasitic resistance. The variable current purposefully uses the parasitic resistance of the line, which can then be received with little delay and attenuation at the destination electronic subsystem.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved signaling system and method hereof. The signaling system preferably includes a signal generator or transmitter coupled to a signal receiver via a conductor having parasitic loading effects. Parasitic loading by design does not involve capacitors and resistors purposefully placed on the conductor. However, even with capacitors and resistors purposefully placed (i.e., non-parasitic loading occurring), the present signaling system applies. The signal generator can simply be an electronic subsystem that produces an output. That output, regardless of whether it is analog or digital, can change. The amount of change can occur at a very high rate depending on, for example, the frequency of the signal sent into and/or produced from the source electronic subsystem. The variable voltage is then placed onto a source termination or source coupling of the parasitic-loaded conductor. Specifically, the only impedance of consequence to the parasitic-loaded conductor is the RC or RLC parasitic components associated with the conductor. The relatively low impedan

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