Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1982-02-01
1985-06-18
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Data refresh
365202, 365210, G11C 1140
Patent
active
045244316
ABSTRACT:
A memory array using nonvolatile memory elements. Preferably multi-dielectric transistors are used to provide nonvolatile information storage. Good write speed is attained by providing a relatively low barrier to carrier injection. To compensate for the resulting low storage time, periodic refresh logic is provided, so that all cells in the array are refreshed at a given clock period, e.g. one second. To compensate for the changing characteristics of the nonvolatile transistors during their storage lifetime, a reference voltage generator is provided which consists of two nonvolatile memory cells programmed in opposite states, together with a resistive network for averaging their output.
REFERENCES:
patent: 4433395 (1984-02-01), Iyehara et al.
Feger William E.
Haken Roger A.
Comfort James T.
Fears Terrell W.
Hiller William E.
Sharp Melvin
Texas Instruments Incorporated
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