High speed, nonvolatile, electrically erasable memory cell and s

Details High speed, nonvolatile, electrically erasable memory cell and s High speed, nonvolatile, electrically erasable memory cell and s

1983-03-14

1984-03-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365174, G11C 1140

Patent

active

044357907

ABSTRACT:
A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g., +5 volts, such that the PMOS transistors of memory cells located at the intersections of the selected X write lines and the selected Y sense lines assume a relatively positive threshold state.

REFERENCES:
patent: 4399523 (1983-08-01), Gerber et al.

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