High-speed, multiple-port, interleaved cache with arbitration of

Details High-speed, multiple-port, interleaved cache with arbitration of High-speed, multiple-port, interleaved cache with arbitration of

1996-04-29

1998-05-12

Asta, Frank J.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 3, 711118, 711127, 711129, 711131, 711210, G06F 1300

Patent

active

057522600

ABSTRACT:
A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

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