High speed multi-threaded reduced instruction set computer...

Details High speed multi-threaded reduced instruction set computer... High speed multi-threaded reduced instruction set computer...

2011-01-18

2011-01-18

Ellis, Richard (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S228000, C712S215000

Reexamination Certificate

active

07873817

ABSTRACT:
A reduced instruction set computer (RISC) processor includes a processing core, which is arranged to process a software thread. A hardware-implemented scheduler is arranged to receive respective contexts of a plurality of software threads, to determine a schedule for processing of the software threads by the processing core, and to serve the contexts to the processing core in accordance with the schedule.

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