High speed, multi-port memory cell utilizable in a BICMOS memory

Details High speed, multi-port memory cell utilizable in a BICMOS memory High speed, multi-port memory cell utilizable in a BICMOS memory

1991-09-09

1993-02-23

Dixon, Joseph L.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365177, 365179, 3652256, 36523006, G11C 1100, G11C 1134, G11C 800

Patent

active

051896400

ABSTRACT:
A multi-port memory cell utilizes a storage cell to define complementary data storage nodes. Each read port of the memory cell includes two FETs respectively coupled between one of a pair of complementary data-out lines and a read enable line to isolate the read ports. Each of the gates of the two read port FETs is connected to one of the corresponding data storage nodes. The storage cell is read by pulling current from the read enable line and monitoring the difference between the complementary data-out lines.

REFERENCES:
patent: 4447891 (1984-05-01), Kadota
patent: 4616347 (1986-10-01), Bernstein
patent: 4623970 (1986-11-01), Allen et al.
patent: 4701883 (1987-10-01), Wrathall et al.
patent: 4768172 (1988-08-01), Sasaki
patent: 4817051 (1989-03-01), Chang
patent: 4833648 (1989-05-01), Scharrer et al.
patent: 4933899 (1990-06-01), Gibbs

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