High speed memory with row redundancy

Details High speed memory with row redundancy High speed memory with row redundancy

1990-02-12

1991-10-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, 371 103, G11C 1300

Patent

active

050580701

ABSTRACT:
A high speed memory with row redundancy has a plurality of memory cells arranged in rows, with additional redundant rows. When a defect is detected in a row, a redundant row is used in place of the defective row. Each row select signal is decoded by a predecoder, receiving a row address, and a decoder, comprising a NOR gate and an output driver. The NOR gate performs a logical NOR on a set of predecoded signals. The output driver receives the output of the NOR gate and has a bipolar portion and a CMOS portion to provide a row select signal, with a fast rise time and with a CMOS voltage level, to each of a plurality of memory blocks. A defective row is deselected by blowing two fuses which are internal to the NOR gate. The fuses are placed adjacent to each other so that the two fuses may be blown in a single operation.

REFERENCES:
patent: 3245051 (1966-04-01), Robb
patent: 4587638 (1986-05-01), Isobe et al.
patent: 4862417 (1989-08-01), List et al.

Affiliated with

Also associated with

Rating

High speed memory with row redundancy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed memory with row redundancy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed memory with row redundancy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-996376