Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1997-12-31
2002-07-02
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S168000, C711S141000, C710S020000
Reexamination Certificate
active
06415364
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory units within a large scale symmetrical multiprocessor system, and, more specifically, to a high-performance memory having integrated directory and data subsystems that allow for the interleaving of memory requests to a single memory unit.
2. Description of the Prior Art
Data processing systems are becoming increasing complex. Some systems, such as Symmetric Multi-Processor (SMP) computer systems, couple two or more processors to shared memory. This allows multiple processors to operate simultaneously on the same task, and also allows multiple tasks to be performed at the same time to increase system throughput.
Although multi-processor systems with a shared main memory may allow for increased throughput, substantial design challenges must be overcome before the increased parallel processing capabilities may be leveraged. For example, the various processors in the system must be able to access memory in a timely fashion. Otherwise, the memory becomes a bottle neck, the processors may spend large amounts of time idle while waiting for memory requests to be processed. This problem becomes greater as the number of processors sharing the same memory increases.
One common method of solving this problem involves providing one or more high-speed cache memories that are more closely-coupled to the processors than the main memory. For example, a cache memory could be coupled to each processor. Information from main memory that is required by a processor during a given task may be temporarily stored within its respective cache so that many requests to memory will be off-loaded. This reduces requests to main memory to a number that is manageable, and allows memory latency to be reduced to acceptable levels.
When multiple cache memories are coupled to a single main memory for the purpose of temporarily storing data signals, some system must be utilized to ensure that all processors are working from the same (most recent) copy of the data. For example, if a copy of a data item is stored, and subsequently modified, in a cache memory, another processor requesting access to the same data item must be prevented from using the older copy of the data item stored either in main memory or the requesting processor's cache. This is referred to as maintaining cache coherency. Maintaining cache coherency becomes more difficult as more caches are added to the system since more copies of a single data item may have to be tracked.
Many methods exist to maintain cache coherency. Some earlier systems achieve coherency by implementing memory locks. That is, if an updated copy of data existed within a local cache, other processors were prohibited from obtaining a copy of the data from main memory until the updated copy was returned to main memory, thereby releasing the lock. For complex systems, the additional hardware and/or operating time required for setting and releasing the locks within main memory becomes too large a burden on through-put to be acceptable. Furthermore, reliance on such locks directly prohibits certain types of applications such as parallel processing.
Another method of maintaining cache coherency is shown in U.S. Pat. No. 4,843,542 issued to Dashiell et al., and in U.S. Pat. No. 4,755,930 issued to Wilson, Jr., et al. These patents discuss a system wherein each processor has a local cache coupled to a shared memory through a common memory bus. Each processor is responsible for monitoring, or “snooping”, the common bus to maintain currency of its own cache data. These snooping protocols increase processor overhead, and are unworkable in hierarchical memory configurations that do not have a common bus structure. A similar snooping protocol is shown in U.S. Pat. No. 5,025,365 to Mathur et al., which teaches local caches that monitor a system bus for the occurrence of memory accesses which would invalidate a local copy of data. The Mathur snooping protocol removes some of overhead associated with snooping by invalidating data within the local caches at times when data accesses are not occurring; however, the Mathur system is still unworkable in memory systems without a common bus structure.
Another method of maintaining cache coherency is shown in U.S. Pat. No. 5,423,016 to Tsuchiya, assigned to the assignee of this invention. The method described in this patent involves providing a memory structure utilizing a “duplicate tag” with each cache memory. The duplicate tags record which data items are stored within the associated cache. When a data item is modified by a processor, an invalidation request is routed to all of the other duplicate tags in the system. The duplicate tags are searched for the address of the referenced data item. If found, the data item is marked as invalid in the other caches. Such an approach is impractical for distributed systems having many caches interconnected in a hierarchical fashion because the time requited to route the invalidation requests poses an undue overhead.
For distributed systems having hierarchical memory structures, a directory-based coherency system has been found to have advantages. Directory-based coherency systems utilize a centralized directory to record the location and the status of data as it exists throughout the system. For example, the directory records which caches have a copy of the data, and further records if any of the caches have an updated copy of the data. When a processor makes a request to main memory for a unit of data, the central directory is consulted to determine where the most recent copy of that unit of data resides so that it may be returned to the requesting processor and the older copy may be marked invalid. The central directory is then updated to reflect the new status for that unit of memory. A novel system and method for performing a directory-based coherency protocol in a Symmetrical Multi-Processor (SMP) system is described in the co-pending application entitled “A Directory-Based Cache Coherency, System”, filed Nov. 5, 1997, Ser. No. 08/965,004 which is incorporated herein by reference in its entirety.
Implementing high-speed memory systems that are capable of supporting a directory-based coherency protocol is problematic for several reasons. In general, accessing the central directory involves a read-modify-write operation. That is, generally, directory information is read from the directory, modified to reflect the fact that new status associated with the data item is being delivered to the requesting processor, and is written back to the directory. This read-modify-write operation cannot be completed as fast as the (single) associated data access to memory. Thus, another data access may not be initiated until the associated read-modify-write operation is complete and memory throughput is therefore diminished.
Prior art systems attempted to make this longer directory latency transparent to the overall system operation by implementing the central directory using faster hardware technology. For example, the memory array used to implement the central directory was implemented using faster Static Random Access Memory (SRAM) devices, whereas the memory array used to implement the data storage was designed using slower, but more dense, Dynamic Random Access Memory (DRAM) devices. This creates practical problems. Because SRAM devices are not as dense as DRAMs, a disproportionally large amount of circuit board area is consumed to implement the directory storage. Moreover, SRAMs and DRAMs have different power and other electrical considerations, adding to the complexity associated with designing, placing, and routing an operational printed circuit card. Additionally, two types of RAM devices must be stocked, then handled during the board-build process making fabrication of the printed circuit card a more difficult and expensive process. Implementing both the directory and data memory arrays using the same logic is practically much more desirable, but would result in a decrease in overall system throughput.
Another pr
Bauman Mitchell A.
Rodi Eugene A.
Atlass Michael B.
Bataille Pierre Michel
Johnson Charles A.
Kim Matthew
Starr Mark T.
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