High speed memory sense amplifier with noise reduction

Details High speed memory sense amplifier with noise reduction High speed memory sense amplifier with noise reduction

1992-09-21

1993-12-21

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Noise suppression

365207, 365208, 307542, G11C 700

Patent

active

052726746

ABSTRACT:
A read circuit for a semiconductor memory that includes a pass transistor between the output of a first sense amplifier reading the memory and a latch. The pass transistor blocks transmission of the sense amplifier's output to the latch whenever a noise glitch producing condition is sensed. A second sense amplifier connected through the same conductive line to the memory cell array as the first sense amplifier has a faster response and lower current threshold in order to detect the glitch producing condition. A pulse generator receives the output of the second sense amplifier and provides a control signal pulse of predetermined duration following detection of the glitch producing condition by the second sense amplifier. The pulse is received by a control gate of the pass transistor, turning the transistor off during the duration of the pulse.

REFERENCES:
patent: 4827454 (1989-05-01), Okazaki
patent: 4959816 (1990-09-01), Iwahashi et al.
patent: 4982366 (1991-01-01), Takemae
patent: 5200926 (1993-04-01), Iwahashi et al.

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