High-speed memory readout circuit using a single set of data buf

Details High-speed memory readout circuit using a single set of data buf High-speed memory readout circuit using a single set of data buf

1994-03-31

1995-02-28

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36518905, 36523008, G11C 700

Patent

active

053943643

ABSTRACT:
In a memory readout circuit, a data register is provided for storing data bits of a word read out of a memory cell array. Connected to the data register is a transfer gate array which is equally divided into groups of first to k-th transfer gates. First to k-th data buffers are connected respectively to the first to k-th transfer gates of different groups. One of the groups of transfer gates is selected and the transfer gates of the selected group transfers first to k-th data bits of unit data from the data register to the first to k-th data buffers, respectively. From the data bits stored in the data buffers, i-th to k-th data bits (where i is in a range from 1 to k) are selected. If i is not equal to k, the stored i-th to (k-1)th data bits are read out of the buffers to an external circuit and the k-th data bit is stored into a latch when the (k-1)th data bit is read out to the output and reads out the k-th data bit from the latch circuit to the external circuit when data bits of subsequent unit data are transferred to the data buffers. If i is equal to k, the k-th data bit is read out of the buffer to the external circuit when data bits of subsequent unit data are transferred to the data buffers.

REFERENCES:
patent: 4831590 (1989-05-01), Ichinose
patent: 5146428 (1992-09-01), Tanimura
patent: 5319595 (1994-06-01), Sarnwatari

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