High speed memory output circuitry and methods for implementing

Details High speed memory output circuitry and methods for implementing High speed memory output circuitry and methods for implementing

1997-02-26

1998-05-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

36518905, G11C 700

Patent

active

057516499

ABSTRACT:
Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit. The amplified data signal provides a fast turnoff to the pull up or pull down transistor, to thereby generate a rapid output at an output node coupled to the other pull up or pull down transistor.

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patent: 5625586 (1997-04-01), Yamasaki et al.
patent: 5636161 (1997-06-01), Mann

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