High speed memory interface for video teleconferencing applicati

Static information storage and retrieval – Read/write circuit – Sipo/piso

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36523003, G11C 1300

Patent

active

053696174

ABSTRACT:
A high speed memory interface, contained within a video teleconferencing system, couples a capture first-in first-out (FIFO) device, a host FIFO, a PB FIFO, and a display FIFO to a high speed memory. The interface includes a high speed channel interface, including an arbiter, that allocates bandwidth for the high speed memory for a display service, a capture service, a host service and a refresh service. The capture FIFO receives raw capture video data, buffers the raw capture video data at a capture rate, and transfers the raw capture video data to the high speed memory. The host FIFO receives display video data from a remote source, buffers the display video data, and transfers the input display video data to the high speed memory. The PB FIFO reads capture video data and display video data, during the PB service, from the high speed memory to provide an input queue for video compression and video decompression. The display FIFO receives, during the display service, display video data from the high speed memory, and buffers the display video data to provide the display video data at a display rate for the host. The high speed memory interface has application for use in a computer system supporting video teleconferencing.

REFERENCES:
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3962689 (1976-06-01), Brunson
patent: 4581721 (1986-04-01), Gunawardana
patent: 4608678 (1986-08-01), Threewitt
patent: 4633441 (1986-12-01), Ishimoto

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