High speed memory cloner with extended cache coherency...

Details High speed memory cloner with extended cache coherency... High speed memory cloner with extended cache coherency...

2005-05-10

2005-05-10

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S165000

Reexamination Certificate

active

06892283

ABSTRACT:
A data processing system comprising a coherency protocol that indicates and updates a coherency state of all data lines within said memory subsystem, and responsive to a naked write operation to a memory location containing a modified copy of data, changes the coherency state of the memory location from modified (M) to invalid (I) without initiating a push of the data to a corresponding address location of main memory. Included within the coherency protocol are specific group of responses for dealing with a naked write request that is received at a memory controller. These responses include: (1) issuing a retry response when the memory controller is unable to allocate a buffer for the write data operation and data at said memory location is not in an M state; (2) issuing a Null response when the memory controller is able to allocate the buffer; and (3) issuing a combined Ack_Resend response when the data at the memory location transitions from an M state to an I state. The Ack_Resend response indicates that the coherency state transition has occurred but the memory controller is not yet able to allocate a buffer to the write operation. The protection of the memory location is transferred to the memory cloner when a combined response is received at the memory cloner for a particular naked write operation.

REFERENCES:
patent: 6128714 (2000-10-01), Onodera
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patent: 6529968 (2003-03-01), Anderson
patent: 6665783 (2003-12-01), Zahir
patent: 6813522 (2004-11-01), Schwarm et al.
patent: 20030153306 (2003-08-01), Study et al.

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