High-speed memory cell with dual purpose data bus

Details High-speed memory cell with dual purpose data bus High-speed memory cell with dual purpose data bus

1976-02-09

1978-05-23

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

307238, 307279, 365190, 365222, G11C 700, G11C 1140

Patent

active

040914615

ABSTRACT:
An improved memory cell for minimizing space consumption and cost of production. A two-rail data bus line configuration is shared for the dual purpose of reading and writing binary information or for powering the memory cell. The memory cell is rendered in a dynamic condition for reading or writing binary information via the data bus lines. At all other times, the memory cell is rendered in a static or holding condition during which time the data nodes of the cell are connected to a source of reference potential and the memory cell is powered.

REFERENCES:
patent: 3564300 (1971-02-01), Henle
patent: 3573485 (1971-04-01), Ballard
patent: 3686645 (1972-09-01), Brojdo
patent: 3849675 (1974-11-01), Waaben
patent: 3949383 (1976-04-01), Askin et al.
patent: 3949385 (1976-04-01), Sonoda
"Sapphire Brings Out The Best In C-Mos", by S. Sheffield Eaton, Electronics/June 12, 1975, pp. 115-118.

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