Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-01-05
2001-09-04
Bragdon, Reginald G. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S104000, C711S108000, C711S154000
Reexamination Certificate
active
06286076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic devices, and more particularly to a high-speed memory-based buffer, and system and method for use thereof.
2. Description of the Related Art
Semiconductor processing has reached the level of placing tens of millions of transistors on a single integrated circuit or monolithic substrate, also known as a chip. The drive towards miniaturization is evident from recent forecasts from chipmakers towards shrinking transistor size from 0.25 micron down to 0.18 micron and beyond in the next decade. It is anticipated that this trend towards increased miniaturization will continue. This drive towards integration of electronic devices on increasingly complex chips requires increasingly compact designs even for relatively simple electronic devices. A companion concern to size is power consumption, as a high power device compacted into a smaller area may cause heating problems on the chip, as well as the possibility of actually melting the chip during operation.
Hardware buffers are devices that receive bits, store the bits temporarily, and then provide the bits upon request thereof. Buffers are often shared by a number of other devices that operate at different speeds or with different sets of priorities. The buffer allows faster devices to operate on the data stream without being held up by slower devices. Buffers are often categorized by the order in which the buffer provides data as compared to the order in which the data are stored. Examples of buffers include first in, first out buffers, also known as FIFOs; last in, first out buffers, as known as LIFOs or stacks, as well as queues, reorder buffers, reservation stations; etc. Another important factor is the size of the buffer, including the depth (i.e. the number of different data entries which can be stored concurrently) as well as the width (i.e. the number of bits that can be comprised in a single data entry).
Hardware buffers are often comprised of memory cells or registers. Memory cells may be comprised of any type of memory, including random access memory (RAM) in any of its varieties. Some memory types are fast on the write-in to read-out turnaround, having high power consumption and a large footprint, i.e. they require a large number of basic components and therefore a large area of semiconductor on a wafer. Other memory types have low power consumption and take up little space but are relatively slow. Registers usually fall into the same category as fast memory. When a buffer is comprised of registers or fast memory, the depth and width of the buffer is severely constrained due to the power consumption and footprint. When a buffer is comprised of slow memory, the speed of the buffer is severely constrained.
It would be desirable to have a buffer with a small footprint on the chip and low power consumption, yet has a rapid turnaround time for data entries written into it. Preferably, the turnaround time should have no latency, that is, data entries should be accepted into the buffer on each clock cycle until the buffer can no longer accept data entries and data entries should be available to be read out on each clock cycle until the buffer is empty. The buffer should also be relatively deep and wide as a function of the footprint and power consumption.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system and method for buffering data entries using a memory and one or more registers, where control logic controls the operations of the memory and the registers. The memory may provide for relatively deep and wide storage of data entries, while minimizing footprint and power consumption. The registers may ensure that a data entry may be written in and/or read out on each clock cycle.
In one embodiment, a buffer configured to store a plurality of data entries comprises a memory, one or more registers coupled between an output of the memory and an output of the buffer, and control logic coupled to the registers and to the memory. The memory and each of the registers are configured to store data entries in data entry storage locations. The control logic is configured to control the operations of the buffer. The combination of memory with the one or more registers coupled between an output of the memory and an output of the buffer may advantageously result in a small footprint and low power consumption. The speed of the registers is added to the high depth and width to size ratio of the memory.
In another embodiment, the number of registers in the buffer is determined number of clock cycles of read latency of the memory. An alternative description is that the number of registers in the buffer is determined by the number of clock cycles between the clock cycle when a data entry is requested from the memory and the clock cycle when the data entry is available at the output of the memory. The number of registers may be set to optimize the speed gain from the use of registers, while minimizing the size and power consumption to depth and width ratio. The memory preferably provides the majority of the data entry storage locations.
In various embodiments, the buffer may be configured as a FIFO buffer or as a LIFO buffer. In one embodiment, the buffer is configured to operate as either a FIFO buffer or a LIFO buffer according to a configuration bit which is set in the control logic.
A method is likewise contemplated, operating within a buffer including a memory and one or more registers chained from the output of the memory. The method comprises reading a first data entry out of the memory and into an output register, the buffer receiving a read request, and providing the first data entry from the output register in response to the buffer receiving the read request. The method may advantageously use the speed of the registers coupled with the depth of the memory, all within a small footprint with relatively low power consumption. The method may further include reading a second data entry out of the memory and into the output register in response to providing the first data entry from the output register. It is noted that this further embodiment primes the output register in preparation for an additional read request during a following clock cycle.
In one embodiment, the method operates in a buffer including at least two registers, the output register, and an intermediate register coupled between the memory and the output register. The method then may further comprise reading a second data entry out of the memory and into the output register in response to providing the first data entry from the output register. In this embodiment, the method further reads a third data entry out of the memory and into the intermediate register after reading the second data entry out of the memory and into the output register.
A system is further contemplated, comprising, in one embodiment, a plurality of buffers coupled between one or more output ports and a plurality of input ports. The output ports are coupled to receive data from the input ports. The buffers may be of any embodiment described herein, but are preferably FIFO buffers, with each of the buffers configured to accept data from a respective input port. The control logic of each buffer is configured to output an empty control signal when the buffer is empty of data entries. Input multiplexers are coupled to each of the input ports and to an output of the respective buffer. The empty control signal from the respective buffer selects between data from the respective input port and the respective buffer. An output multiplexer is coupled to receive data from the input multiplexers and to provide output data to a respective output port. The depth of the buffers may advantageously provide for better buffering of data in the system without using unnecessary space or power.
REFERENCES:
patent: 4616338 (1986-10-01), Helen et al.
patent: 4628477 (1986-12-01), Burrows
patent: 4833655 (1989-05-01), Wolf et al.
patent: 5032985 (1991-07-01), Curran et al.
patent: 5325487 (1994-06-01),
Bragdon Reginald G.
Conley Rose & Tayon PC
Merkel Lawrence J.
Sun Microsystems Inc.
LandOfFree
High speed memory-based buffer and system and method for use... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed memory-based buffer and system and method for use..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed memory-based buffer and system and method for use... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2435470