High speed low skew CMOS to ECL converter

Details High speed low skew CMOS to ECL converter High speed low skew CMOS to ECL converter

1999-01-29

2001-01-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S066000, C326S077000, C326S062000, C326S063000, C326S121000, C327S333000

Reexamination Certificate

active

06175249

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for transmitting electrical signals from one location to another. In particular, the present invention relates to converters for changing the logic levels associated with the operation of Complementary Metal-Oxide-Silicon (CMOS) transistors to the logic levels associated with the operation of emitter-coupled logic (ECL) transistors.
2. Description of the Prior Art
A voltage level converter is used to adjust the logic high and logic low voltage levels associated with a single input signal, or a pair of input signals, coming into the converter to high and low voltage levels compatible with downstream circuitry. The converter must transfer these electrical signals at desired amplitude and rate. The signal transfer occurs between active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some distance from one another. One example of a proximate device interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote device interface requiring one or more bus connections is the coupling of one computing system to another.
A continuing goal in all computing and communication systems is to be able to transfer electrical signals accurately and as quickly as possible. In order to achieve that goal, it is important that those signals are transmitted at relatively uniform rates, amplitudes, and strengths. This is more likely to occur within a single computing system, less so when interfacing of a plurality of non-uniform computing systems is involved.
It is well known that in digital systems the signals moving between devices are categorized as either logic level high (or “1” or “ON”) and logic level low (or “0” or “OFF”). The particular signal potential that defines whether a logic high or a logic low is being transmitted is dependent upon the semiconductor components that form the circuitry associated with that transmission. The most common circuit configurations used to produce digital signals include, among others, CMOS, Transistor-Transistor Logic (TTL), and ECL—positive power rail-based ECL (PECL) in particular. Each of these logic configurations operates differently as a function of the “swing” between what constitutes a logic high signal and what constitutes a logic low signal.
For CMOS logic, which is based primarily on the use of slower, less-power-consuming MOS transistors, a logic low signal is generally developed in the range of 0.6 volts (V) above a low-potential power rail GND, which may be at 0.0 V. A logic high signal is generally developed in the range of Vcc to Vcc-0.6 V, where Vcc may vary between 4.5 V and 5.5 V for a nominal 5-volt supply, or between 3.0 V and 3.6 V for a nominal 3.3-volt supply. For a 3.3-volt supply then, the differential swing between low and high must be at least 2.4 volts in order to ensure that a desired shift between a logic low and a logic high will occur. TTL and ECL logic configurations, on the other hand, are based primarily on the use of faster, high-power-consuming bipolar transistors. The differential swing for a shift between a logic low and a logic high is significantly less than it is for CMOS operation—it may as low as 0.4 volt. In PECL circuitry, which is Vcc dependent, a logic high is equivalent to a potential of about Vcc-0.8 V and a logic low is equivalent to a potential of about Vcc-1.9 V. Thus, in mating CMOS and non-CMOS transmissions, it can be seen that variations in potential swings will not automatically ensure the triggering of a desired swing from one logic level to another. Furthermore, minor potential swings in CMOS signals may not effect any logic level change therein; however, they may be significant enough to cause an unexpected change in a TTL or an ECL logic value when transmitted to a TTL-or an ECL-based system.
Clearly, unexpected changes in logic values are not desirable. They can cause significant operational errors. Therefore, it is important to provide a logic level converter that will not generate excessive signal potential swings—other than those specifically desired to achieve a logic level shift. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. The extent of the oscillation is dependent upon the particular transistor system used as well as the loading of the downstream-coupled circuit.
As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the corresponding differential swings associated with their logic outputs are reduced. When the wider-swing CMOS logic systems interface with smaller-swing bipolar-transistor-based logic systems the noise associated with CMOS operation may generate enough of a swing to cause an undesired transistor switching. The signal bounce that occurs with the rapid switching often creates reflections in transmission media. It is therefore important to minimize distortions associated with signal switches. However, efforts to minimize distortions can result in increased signal propagation delays—an undesirable condition in smaller, faster systems. It is also to be noted that with increasingly smaller devices, the effects of fabrication vagaries on signal distortion are magnified. Therefore, to the extent such vagaries can be neutralized, the logic level conversion can be achieved without sacrificing transmission rates.
CMOS-to-ECL converters are well known. Examples of prior converters include the circuits disclosed in U.S. Pat. No. 5,343,093 issued to Tran, U.S. Pat. No. 5,311,082 issued to Lam, and U.S. Pat. No. 5,117,134 issued to Aso. Each of the noted prior devices provides for shifting of the logic levels associated with both of the complementary signals associated with the converter. To that end, they subject both signals to undesirable distortions that can occur during signal transitions. In addition, the Lam converter is referenced to the high-potential power rail and more susceptible to temperature, fabrication, and Vcc changes affecting signal amplitude and transmission rate. The Aso circuit requires an extra switching branch in order to adjust for common-mode effects associated with the MOS-level potentials. An added branch such as this increases the size of the converter—an undesirable prospect when smaller devices are of importance.
Therefore, what is needed is a logic level converter that can translate MOS-level signals into ECL-level signals with minimum propagation delay and little distortion. What is also needed is a logic level converter that is relatively independent of temperature, fabrication, and Vcc vagaries. Further, what is needed is a logic level converter that is relatively simple to fabricate and that does not take up excess chip space.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a logic level converter that can translate MOS-level signals into ECL-level signals with minimum propagation delay and little distortion. It is also an object of the present invention to provide such a logic level converter that is relatively independent of temperature, fabrication, and Vcc vagaries. Another object of the present invention is to provide a logic level converter that is relatively simple to fabricate and that does not take up excess chip space.
These and other objectives are achieved in the present invention by establishing one of the two complementary outputs of the converter as a fixed reference signal. That is, one output of the converter remains at a set poten

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