High speed, low-power nibble mode circuitry for dynamic memory

Details High speed, low-power nibble mode circuitry for dynamic memory High speed, low-power nibble mode circuitry for dynamic memory

1984-08-29

1987-08-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365189, 365193, G11C 1140

Patent

active

046850899

ABSTRACT:
A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and the latched address includes the address of the starting bit within the 4-bit sequence for serial I/O. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence. To reduce power dissipation, the inverter stages of the ring counter are operated by pulsed clocks generated from the asynchronous memory control clocks received from the CPU.

REFERENCES:
patent: 4567579 (1986-01-01), Patel et al.

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