Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-06-29
2001-05-22
Nguyen, Matthew V. (Department: 2838)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
Reexamination Certificate
active
06236234
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit and, more particularly, to an interface circuit with a tri-state buffer incorporated in a semiconductor integrated circuit device.
DESCRIPTION OF THE RELATED ART
A standard tri-state buffer is usually incorporated in the peripheral circuit of a microcomputer. The standard tri-state buffer is changed between high impedance state and low impedance state. When a data signal is output from or input into the microcomputer, the standard tri-state buffer is changed to the low impedance state, and the transfers digital data signals between an internal bus and an external bus system in a time division multiplexing fashion. However, if the standard tri-state buffer is changed to the high impedance state, the internal bus is electrically isolated from the external bus system, and any digital data signal is not permitted to pass through the standard tri-state buffer. A large amount of parasitic capacitance is usually coupled to the external bus system, and the standard tri-state buffer swings the data signals in a relatively narrow potential range.
The standard tri-state buffer has a control node, a data input node and a data output node. A control signal representative of the high impedance state or the low impedance state is supplied to the control node so as to change the standard tri-state buffer between the high impedance state and the low impedance state. While the standard tri-state buffer is operating in the low impedance state, the standard tri-state buffer is responsive to the digital data signal at the input node so as to change the logic level at the output node thereof.
An open-drain type tri-state buffer fixes the output node to a high voltage level in the high impedance state. The output node is connected through a pull-up resistor to a power supply line, and the output node is pulled up to the power voltage level in the high impedance state.
The tri-state buffer may be connected to an external circuit powered with a power voltage lower than the power voltage therein. The tri-state buffer changes the output node to the low power voltage in response to the digital data signal of the high level.
FIG. 1
shows a typical example of the input/output interface circuit. An internal control terminal
1
, an internal data input terminal
2
, an external signal terminal
3
and an internal data output terminal
4
are associated with the prior art input/output interface circuit. The prior art input/output interface circuit is broken down into a signal input circuit
18
and a signal output circuit
20
.
The signal input circuit
18
is connected between the external signal terminal
3
and the internal data output terminal
4
, and responsive to the potential level at the external signal terminal
3
so as to change the internal data output terminal
4
between the two potential levels corresponding to the two logic levels.
The signal output circuit
20
is implemented by the prior art standard tri-state buffer. The prior art tri-state buffer includes a complementary inverter, i.e., a series combination of a p-channel enhancement type field effect transistor
11
and an n-channel enhancement type field effect transistor
12
, a two-input NAND gate
13
, a two-input AND gate
14
and an inverter
16
. The complementary inverter
11
/
12
is connected between a power voltage line VDD
2
and a ground line VSS, and the external signal terminal
3
is connected to the common drain node between the p-channel enhancement type field effect transistor
11
and the n-channel enhancement type field effect transistor
12
. The power supply line VDD
2
is lower in potential level than a main power supply line (not shown) connected to the two-input NAND gate
13
, the two-input AND gate
14
and the inverter
16
.
The internal control terminal
1
is directly connected to one input node of the two-input NAND gate
13
and one input node of the two-input AND gate
14
. The internal data input terminal
2
is directly connected to the other input node of the two-input NAND gate
13
, and is connected through the inverter
16
to the other input node of the AND gate
14
. The output node of the two-input NAND gate
13
is connected to the gate electrode of the p-channel enhancement type field effect transistor
11
, and the output node of the two-input AND gate
14
is connected to the gate electrode of the n-channel enhancement type field effect transistor
12
.
The signal output circuit
20
behaves as follows. When a control signal changes the internal control terminal
1
to a low voltage level, the two-input NAND gate
13
and the two-input AND gate
14
are disabled with the low voltage level at the internal control terminal
1
, and fix the output nodes to a high voltage level and a low voltage level, respectively. The high voltage level and the low voltage level are supplied to the gate electrode of the p-channel enhancement type field effect transistor
11
and the n-channel enhancement type field effect transistor
12
, respectively, and both field effect transistors
11
/
12
are turned off. Thus, the signal output circuit
20
or the prior art standard tri-state buffer enters the high impedance state in the presence of the control signal of the low voltage level.
When the control signal is changed to the high voltage level, the two-input NAND gate
13
and the two-input AND gate
14
are enabled with the high voltage level, and become responsive to the potential level at the internal input terminal
2
.
If the internal input terminal
2
is in the high voltage level, the high voltage level is directly supplied to the two-input NAND gate
13
, and the two-input NAND gate
13
changes the output node to the low level. On the other hand, the inverter
16
supplies the low voltage level to the two-input AND gate
14
, and the two-input AND gate
14
changes the output node to the low voltage level. With the low voltage level, the p-channel enhancement type field effect transistor
11
turns on, and the p-channel enhancement type field effect transistor
12
turns off. Thus, the power supply line VDD
2
is connected through the p-channel enhancement type field effect transistor
11
to the external signal terminal
3
, and an output signal of the high voltage level VDD
2
is supplied from the external signal terminal
3
to the external bus system.
If the internal input terminal
2
is in the low voltage level, the low voltage level is directly supplied from the internal input terminal
2
to the two-input NAND gate
13
, and the two-input NAND gate
13
changes the output node to the high voltage level. With the high voltage level, the p-channel enhancement type field effect transistor
11
turns off, and the external signal terminal
3
is electrically isolated from the power supply line VDD
2
. On the other hand, the inverter
16
supplies the high voltage level to the two-input AND gate
14
, and the two-input AND gate
14
changes the output node to the high voltage level. With the high voltage level, the n-channel enhancement type field effect transistor
12
turns on, and the external signal terminal
3
is connected through the n-channel enhancement type field effect transistor
12
to the ground line VSS. The output signal is changed to the low voltage level.
The signal output circuit
20
changes the external signal terminal
3
between the power voltage level VDD
2
and the ground level VSS in the low impedance state, and the output signal is swung in the narrow potential range.
Turning to
FIG. 2
of the drawings, another prior art input/output interface circuit is also broken down into a signal input circuit
18
and a signal output circuit
22
. The signal input circuit
18
is similar to that of the prior art input/output interface circuit shown in
FIG. 1
, and no further description is incorporated hereinbelow for avoiding repetition. However, the signal output circuit
22
is implemented by the prior art open-drain type tri-state buffer.
The signal output circuit
22
includes an n-channel enhancement typ
McGuireWoods LLP
NEC Corporation
Nguyen Matthew V.
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