Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-12
2005-04-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C326S033000, C326S041000, C326S047000, C326S101000, C327S051000, C327S309000, C327S321000, C365S185130, C711S102000, C711S104000, C711S118000
Reexamination Certificate
active
06880144
ABSTRACT:
A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a plurality of memory cells. Each of the memory cells is coupled to respective bitline columns. The circuit further includes a sensed output from one of the bitline columns, and a global bitline coupled to a same respective bitline column of each of the plurality of sub-arrays. Each global bitline includes a voltage swing limiter for limiting a voltage swing of the global bitline, and an n-type transistor. The n-type transistor has a gate, a first terminal, and a second terminal. The gate is coupled to the sensed output, the first terminal is coupled to the global bitline, and the second terminal is coupled to the voltage swing limiter.
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Kik Phallaka
Martine & Penilla & Gencarella LLP
Smith Matthew
Sun Microsystems Inc.
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