Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-04-09
2002-09-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S026000, C326S027000
Reexamination Certificate
active
06445212
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90100700, filed Jan. 12, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an output device. More particularly, the present invention relates to an output device capable of increasing both driving capacity and small voltage slew rate and permitting on-chip programming through a storage unit. Ultimately, the output device has an output impedance, a driving capacity, a voltage slew rate, and an output waveform closer to the desired specifications.
2. Description of Related Art
In high-speed integrated circuit designs, the driving capacity, the matching of output impedance and other specifications such as the voltage slew rate of an output buffer is very important. To obtain a better design, a number of ways have been developed, for example, in U.S. Pat. No. 5,974,476 and 5,162,672. However, these methods cannot support a high driving capacity small output impedance and a low driving capacity small voltage slew rate at the same time. In addition, the output waveform is highly unsymmetrical due to device characteristics or often leads to a relatively high noise ratio due to unmatched impedance on the transmission line. In U.S. Pat. No. 4,820,942, an output driving circuit that incorporates both AC and DC current is introduced. By combining AC and DC circuits into a single configuration, an AC circuit can be triggered for a pre-defined period according to preset conditions. However this circuit can only attain a fixed driving and delay capacity. Furthermore, since the AC portion of the circuit is in action for a brief period only, overall benefits to output impedance matching is limited.
In brief, the aforementioned circuit designs cannot support a high driving capacity small output impedance, and a low driving capacity small voltage slew rate at the same time. In addition, a mismatch between an externally connected circuit and the output impedance of the buffer may generate unwanted transmission line noise.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an output buffer circuit that supports a high capacity small output impedance and a small driving capacity voltage slew rate for reducing ground bounces and transient voltage drop.
A second object of this invention is to provide a high-speed, low-noise and impedance matched output buffer circuit whose output waveform is symmetrical.
A third object of this invention is to provide a high-speed, low-noise output buffer circuit capable of fine impedance matching so that noise interference due to reflection on a transmission line noise is minimized.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a high-speed, low-noise, impedance-matched programmable multiple configuration output buffer circuit. The output buffer circuit has an input port terminal and an output port terminal. The programmable multiple configuration output buffer circuit at least includes an output buffer stage having no delay unit, and one or more output buffer stages having a delay unit. The output buffer stage having no delay unit includes a first type channel pull up transistor, a second type channel pull down transistor and a first logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together. The drain terminal of the pull up and pull down transistor are also connected to the output port of the programmable multiple configuration output buffer circuit. The first logic circuit receives an enable signal and an input signal. The output buffer stage having a delay unit therein includes a first type channel pull up transistor, a second type channel pull down transistor, and a second logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together. The drain terminal of the pull up and pull down transistor are also connected to the output port. The second logic circuit is connected to the enable signal, the input signal, and a corresponding select enable signal.
This invention may also incorporate a storage device. The storage device can be used for setting the driving capacity of the delay unit inside the output buffer. Furthermore, the setting can be done after chip production so that low yield resulting from processing drifts can be avoided.
In brief, this invention provide an output buffer circuit that supports a high capacity small output impedance and a small driving capacity voltage slew rate simultaneously. In the meantime, a symmetrical output waveform can be produced and output impedance can be adjusting to match a transmission line so that noise is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4820942 (1989-04-01), Chan
patent: 5528166 (1996-06-01), Iikbahar
patent: 6066958 (2000-05-01), Taniguchi et al.
Chin Chu Yu
Wey Meng-Jer
Faraday Technology Corp.
J.C. Patents
Tokar Michael
Tran Anh Q.
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