High speed-low cost, clock controlled CMOS logic implementation

Details High speed-low cost, clock controlled CMOS logic implementation High speed-low cost, clock controlled CMOS logic implementation

1974-10-09

1976-09-21

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307207, 307215, H03K 1908, H03K 1936

Patent

active

039821382

ABSTRACT:
A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification stage, where such is required.

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patent: 3825888 (1974-07-01), Kawagoe
boleky et al., "High-Performance Low-Power CMOS Memories Using SOS Technology"; Reprinted from IEEE J. Solid-State Circuits, Vol. SC-7, pp. 135-145, 4/1972: Semiconductor Memories, IEEE Press, 1972.
Surgent, "Insulated Gate Field-Effect Transistor Sense Amplifier Latch"; IBM Tech. Discl. Bull.; Vol. 13, No. 9, pp. 2670-2671; 2/1971.
Cole et al., "Logic Gate", IBM Tech. Discl. Bull.; Vol. 16, No. 2, p. 566; 7/1973.
Cole et al., "Dynamic Logic Gate"; IBM Tech. Discl. Bull.; Vol. 16, No. 2, p. 567; 7/1973.

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