High speed, low clock load register dump circuit

Details High speed, low clock load register dump circuit High speed, low clock load register dump circuit

1996-10-21

1998-06-02

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Current driving

326 17, 326113, 36518905, H03K 190185

Patent

active

057606080

ABSTRACT:
A register dump providing enhanced efficiency by using a transmission gate for generating a register word line signal so as to reduce clock loading, and by using a complementary gate for generating a precharged pull-down signal so as to reduce discharge time and register word line capacitive loading.

REFERENCES:
patent: 4703457 (1987-10-01), Bodenstab
patent: 5255235 (1993-10-01), Miyatake
patent: 5619162 (1997-04-01), Ogihara
patent: 5646892 (1997-07-01), Masuda et al.
patent: 5675529 (1997-10-01), Poole
"Principles Of CMOS VLSI Design, A Systems Perspective", Neil H.E. Weste, AT&T Bell Laboratories and Kamran Eshraghian, University of Adelaide; Addison-Wesley Publishing Company, Reading, MA; Oct., 1985, pp. 54-58, pp. 161-162.

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