High speed logical or circuit

Details High speed logical or circuit High speed logical or circuit

1999-04-07

2001-07-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S112000, C326S119000, C326S104000, C326S106000

Reexamination Certificate

active

06265900

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit, more particularly, to a fast OR logic circuit implemented in integrated circuit form.
BACKGROUND OF THE INVENTION
A conventional CMOS OR circuit (e.g. the 3-input OR circuit
10
of
FIG. 1
) is slow, inhibiting its use in the critical speed path of an Integrated Circuit (IC).
FIG. 2
shows a known 3-input OR circuit
20
, which is undesirably slow when designed to be operable under all temperatures, process corners and supply voltages. Furthermore, the speed of OR circuit
20
varies significantly with temperature, process and supply voltage variations.
FIG. 3
shows a computer simulation of a timing delay between input terminal IN
1
and output terminal OUT of OR circuit
20
, under a nominal operation condition, (i.e. typical process corner, 25° C. and 5 volts supply voltage). Using the midpoint between the positive and the negative supply voltages (i.e. 2.5 volts) to measure the delay, it is seen from
FIG. 3
that a delay of 0.36 nsec exists between the time the input signal IN
1
crosses the 2.5 volts and the time when output signal OUT crosses the same voltage level. The 0.36 nsec delay is undesirably high for some applications.
Therefore a need exists for a CMOS OR circuit which is relatively insensitive to changes in temperature, process and supply voltage variations and operates at a high speed under a nominal operating condition.
SUMMARY OF THE INVENTION
The high-speed CMOS OR circuit, in accordance with one embodiment of the present invention, includes a select transistor for each input signal, a circuit for supplying a fixed current to the common drain terminals of the select transistors and a maximum power sensor circuit for controlling the amount of current that is supplied by a variable current supply to the common drain terminals of the select transistors.
The fixed current supply turns on only when the OR circuit is in a selected state thereby to limit the voltage swing across the common drain and common source terminals of the select transistors and thus to improve the speed of the OR circuit. A delay circuit formed by a string of inverters receives the voltage signal generated at the output terminal of the OR circuit and supplies an inverted voltage signal to a gate terminal of a PMOS transistor to turn on or turn off the fixed current supply.
To ensure that the OR circuit is fast under all process corners, temperatures and voltage supplies, the maximum power sensor senses the voltage signals across the common drain and common source terminals of the select transistors thereby to adjust the amount of current that the variable current supply supplies to the common drain node.


REFERENCES:
patent: 5432463 (1995-07-01), Wong et al.
patent: 5457404 (1995-10-01), Sharpe-Geisler
patent: 5661411 (1997-08-01), Nguyen
patent: 5841300 (1998-12-01), Murabayashi et al.
patent: 5912900 (1999-06-01), Durham et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6046606 (2000-04-01), Chu et al.

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