Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1995-05-17
1997-10-28
Westin, Edward P.
Electronic digital logic circuitry
Interface
Logic level shifting
H03K 19086
Patent
active
056821085
ABSTRACT:
A high speed level translator is disclosed in which an ECL differential input signal is applied to a differential input amplifier, amplified, and converted to a single ended intermediate signal. An inverter circuit receives the intermediate signal and outputs a signal indicative of the polarity of the ECL differential input signal. The differential amplifier is biased with a current source which varies the bias current according to fluctuations in the supply voltage such that the operating point of the differential amplifier is automatically adjusted to compensate for variations in the supply voltage. Adjusting the bias current in such a manner allows for a reduction in power dissipation over conventional level translators. Further, since the differential amplifier is configured to provide a single ended intermediate signal, a current mirror is not required to be connected between the differential amplifier and the inverter. Eliminating the need for such a current mirror is advantageous in reducing the number of gate delays and thereby increasing the speed of the level translator.
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Driscoll Benjamin D.
Integrated Device Technology Inc.
Westin Edward P.
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