High speed lateral heterojunction MISFETs realized by...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

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C257S019000, C257S190000, C257S194000, C438S172000, C438S933000

Reexamination Certificate

active

06927414

ABSTRACT:
A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

REFERENCES:
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 2004/0065927 (2004-04-01), Bhattacharyya
Huang, L.J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding,” 2001 Sympos. on VLSI Tech. Digest of Technical Papers, pp. 57-58.
Feder, B.J., “I.B.M. Finds Way to Speed Up Chips,” The New York Times, Jun. 8, 2001.
Nayfeh, H.M. et al., “Electron Inversion Layer Mobility in Strained-Si n-MOSFET'S with High Channel Doping Concentration Achieved by Ion Implantation,” DRC Conf. Digest, 2002, pp. 43-44.
“Modern Dictionary of Electronics” (Rudolf F. Graf, ed.), 1999, Butterworth-Heinemann division of Reed-Elsevier Group, p. 345.

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