High speed IO buffer

Details High speed IO buffer High speed IO buffer

2006-09-29

2008-11-04

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000

Reexamination Certificate

active

07446558

ABSTRACT:
A bi-directional buffer is provided. The buffer includes a driver, a receiver, and a circuitry configured to select a driving mode in response to detecting a first condition and to select a receiving mode in response to detecting a second condition. The driving mode has a first impedance and the receiving mode has a second impedance. The second impedance is partially contributed from the driver.

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Aklra Kotabe, Kenichi Osada, Naoki Kitai, Mio Fojioka, Shiro Kamohara, Mosahiro Moniwa, Sadayuki Morita, and Yoshikazu Saitoh; A Low Power Four-Transistor SRAM Coil With a Stacked Vertical Poly-Silicon PMOS and a Dual-Word-Voltage Scheme; IEEE Journal of Solid-State Circuits; Apr. 2005; vol. 40, No. 4; pp. 570-576.
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