High speed interrupt controller

Details High speed interrupt controller High speed interrupt controller

2000-03-07

2003-08-12

Auve, Glenn A. (Department: 2189)

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt inhibiting or masking

C710S260000, C710S266000, C710S269000

Reexamination Certificate

active

06606677

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to interrupt servicing mechanisms within computer systems and, more particularly, to a high speed interrupt controller and method for interrupt handling in a data communication system.
2. Description of Related Art
Digital communication over a communication channel is well known in the art. Modem data communication systems often have multiple high performance data processors and generally include a plurality of external devices interconnected by one or more various buses. For example, modern computer systems typically include a system processor coupled through a high bandwidth local expansion bus, such as the peripheral component interconnect (PCI) bus or the VESA (Video Electronics Standard Association) VL bus, to an external shared memory, peripheral devices, and other processors. Examples of devices which can be coupled to local expansion buses include SCSI adapters, network interface cards, video adapters, etc.
High performance bus architectures, such as the PCI bus architecture, provide a hardware mechanism for transferring large sequential groups of data between a peripheral controller's local memory and a system processor's shared memory via burst cycles. In many bus architectures, the maximum burst length is typically not defined.
Systems in which many devices share a common resource, typically utilize arrangements for allocating access to the resource under conditions during which a plurality of associated devices may concurrently request access. High performance systems have the potential to generate multiple independent requests for access to one or more external components, often via a single shared bus interface unit (BIU). Since multiple independent input/output (I/O) requests may appear at the BIU at any given time, the data communication system requires a shared bus arbitration scheme to determine the priority of the I/O requests for accessing the shared bus. In multi-master systems, where one or more data processors have the capability of becoming a bus master, the bus arbitration protocol determines which data processor becomes the bus master first. Typically, these multi-master systems employ an arbiter, external to the data processors, to control the shared bus arbitration, and each data processor requests access to an external shared memory or another external device from the arbiter.
In typical microprocessor systems the bus transports data among the processor and other components. The central processing unit (CPU) is usually the master of the bus, controlling the flow of data to and from the CPU and to the other components of the system, such as printers, memory, displays, and parallel and serial ports. Rather than have the CPU perform complex mathematical calculations, which is very slow, the data may be sent to the dedicated math co-processor where the calculations are performed, freeing the CPU to perform another task. Other masters in a multi-master arrangement may be used for ethernet control as part of a local area network (LAN), video controllers, or some other customized operation.
In a multi-master communication system a system may become hung-up for various reasons and it is necessary to recognize each reason from the type of interrupt received from a particular device. For example, a hang condition could happen due to an unrecognized address on a shared bus, when the system cannot abort the transfer or does not have the ability to ban the bus master from the shared bus. Sometimes a bus master does not give up the shared bus for a long time, thus causing other masters to be unable to proceed with a transfer in time. Other times a condition happening elsewhere in the system makes buffer space or data unavailable for an unacceptable amount of time, so that the bus becomes unusable.
If a bus hang condition occurs on a shared bus within a subsystem of a communication system with several subsystems, so that a transfer operation cannot be completed, it is possible that the entire subsystem will not be able to proceed any further. The subsystem processor may itself be unable to proceed (e.g. is presently attempting to read an address via the hung shared bus) and therefore cannot be used to recover from the hang condition. If the subsystem hang condition must be reset from an external source (i.e., from the system's main computer via a bus external to the subsystem), the loss of information on either transferring data and/or error conditions may occur. It may also result in the subsystem being unable to interact with other subsystems while the recovery is taking place and/or during the time it takes for the external source to realize that a problem has occurred in the subsystem. This may in turn require further recovery efforts to become necessary. In other conventional systems, the entire subsystem has to be reset, via an external source. This not only causes the loss of error/recovery information but may cause additional problems with any other subsystem of the communication system, with which the subsystem getting reset is interfacing.
In most systems, an input/output (I/O) operation can proceed in parallel with processor program execution. Interrupts and interrupt handlers allow the processor to execute a program concurrently with the I/O operation, and be signaled as soon as the I/O operation is completed or unsuccessfully interrupted. An interrupt is a signal sent to the processor alerting it to a significant event, and awaiting to the processor's response. The interrupt stops the currently executing program and transfers control to an interrupt service routine (ISR) or device interrupt handler, which performs some appropriate action. When finished, the ISR returns control of the processor to the interrupted program. The processor subsequently restarts the interrupted program in the same state it was in when the interrupt occurred.
In many systems a processor has a limited number of external interrupt input lines, and may even have only one such line. When it receives interrupts from a plurality of peripheral devices and bus adapters, it takes time to find out the source and reason for the interrupt. In such cases there is a desire for increased processor interrupt handling capability, so that the processor can receive and instantly discriminate interrupts from multiple alert and interrupt sources, within a few processor internal bus cycles.
Therefore, there is a need for a method and a system for expanding the number of interrupts which can be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The method and system should be flexible and compatible with a number of digital processor types, modular and easily expandable, and provide improved operational speed. The system and method should be usable in high performance multi-master data communication systems with multiple shared external devices.
SUMMARY OF THE INVENTION
The foregoing and other objects, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments which makes reference to several drawing figures.
One preferred embodiment of the present invention is a high speed interrupt controller system usable in a multi-master data communication system. The interrupt controller system is capable of extending capabilities of a processor with limited number of interrupt input lines to accommodate and discriminate interrupts and alerts from a plurality of interrupting sources. The system has an interrupt controller connected to the processor via a processor bus and configured to receive a plurality of interrupts and alerts from the plurality of interrupting sources, and to assert an interrupt signal to the processor upon receipt of the interrupt from any of the plurality of interrupting sources. The interrupt controller has a masking register for enabling and disabling the interrupts from the plurality of interrupting sources individually, and a device interru

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