High speed interface with looped bus

Details High speed interface with looped bus High speed interface with looped bus

2005-08-23

2005-08-23

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C710S104000, C711S154000

Reexamination Certificate

active

06934785

ABSTRACT:
A method and associated apparatus is provided for improving the performance of a high speed memory bus by substantially eliminating bus reflections caused by electrical stubs. The stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a looping bus for continuing the looping bus through each device. The invention also provides an interface circuit that enables data communications between devices of different technologies. The interface circuit connects to the looping data bus and includes a circuit for providing voltage level, encoding type, and data rate conversions for data received from the looping data bus and intended for use on a second data bus connected to the interface circuit.

REFERENCES:
patent: 4974152 (1990-11-01), Guiffant et al.
patent: 5081648 (1992-01-01), Herzog
patent: 5452330 (1995-09-01), Goldstein
patent: 5623644 (1997-04-01), Self et al.
patent: 5631906 (1997-05-01), Liu
patent: 6014037 (2000-01-01), Gabara et al.
patent: 6233253 (2001-05-01), Settle et al.
patent: 6286067 (2001-09-01), James et al.
patent: 6356984 (2002-03-01), Day et al.
patent: WO 99/19874 (1999-04-01), None
patent: WO 99/30240 (1999-06-01), None
Yasuhiro Konishi et al., “Interface Technologies for Memories and ASICs—Review and Future Direction—”, IEICE Transactions on Electronics, vol. E82-C. No. 3 Mar. 1999.
Alfredo Moncayo et al., “Physical Layer Design of a 1.6 GB/s DRAM Bus”, 1999 IEEE.
Gustavson, D., “SCIzzL: The Local Area Memory Port,” http://www.scizzl.com, 9 pages, reviewed Oct. 2, 2000.
Gustavson, D. “SCI Industrial Takeup and Future Developments,” http://www.scizzl.com/Perspectives.html, 13 pages, reviewed Oct. 2, 2000.
“Hot Rod™ High-Speed Serial Link Gallium Arsenide,” Gazelle Microcircuits, Inc. pp. 1-35.

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