High-speed interface for high-density flash with two levels...

Details High-speed interface for high-density flash with two levels... High-speed interface for high-density flash with two levels...

2005-07-11

2009-12-29

Song, Jasmine (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S103000, C711S129000, C711S162000, C711S165000

Reexamination Certificate

active

07640398

ABSTRACT:
A memory circuit and a method of operating a flash or EEPROM device that has two levels of internal cache. A memory device having a memory array, sense amplifiers, a data register, cache, an input-output circuit, and a control logic circuit is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.

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