High speed input buffer circuit for low voltage interface

Details High speed input buffer circuit for low voltage interface High speed input buffer circuit for low voltage interface

2000-05-19

2002-09-17

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S077000

Reexamination Certificate

active

06452429

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an input buffer circuit.
2. Description of the Related Art
Digital systems often use both transistor-transistor logic (TTL) semiconductor devices and complementary metal oxide semiconductor (CMOS) devices. Accordingly, such systems require interface circuits between the TTL semiconductor devices and CMOS devices. For example, input buffers (generally referred to as TTL-to-CMOS input buffers or TTL compatible input buffers) are often in CMOS devices for converting TTL input levels into CMOS levels.
As TTL semiconductor devices and CMOS devices operate at a low supply voltage of about 3.3 volts, input buffers in CMOS semiconductor devices convert low voltage transistor-transistor logic (LVTTL) input levels into CMOS levels. In an operation using a low supply voltage of 3.3 volts, an input low voltage (VIL) of 0 volts and an input high voltage (VIH) of 2.8 volts are for typical LVTTL input levels. In the worst case for the LVTTL input levels, the maximum VIL is about 0.8 volts, and the minimum VIH is about 2.0 volts. In general, the input buffers of the CMOS devices need to convert not only the LVTTL levels but also small swing transistor logic (SSTL) level into CMOS levels.
Recent developments of portable information equipment such as portable telephones to which low voltage and power consumption are very important demand input buffers that can support low voltage interfaces, in which the VIL is 0 volts and the VIH is 1.8 volts, and general LVTTL interfaces, in which the VIL is 0 volts and the VIH is 2.8 volts. The conventional N differential amplification type input buffer shown in FIG.
1
and the conventional P differential amplification type input buffer shown in
FIG. 2
do not simultaneously support the low voltage interface of 1.8 volts and the LVTTL interface of 2.8 volts. Therefore, to simultaneously support the low voltage interface and the LVTTL and SSTL interfaces, self-biased differential amplification type input buffers were introduced. A representative self-biased differential amplification type input buffer is described by M. Bazes [Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers, IEEE Journal of Solid-State Circuits, Vol. 26, pp. 165-169, February 1991]. Also, the improved self-biased differential amplification type input buffer as shown in
FIG. 3
is described by Yasuhiro Takai and Mamoru Fujita [A 250 Mbps/pin, 1 Gb Double Data Rate SDRAM with a Bidirectional Delay and an Inter-bank shared Redundancy Scheme, ISSCC Digest of Technical Papers, February 1999].
In the self-biased differential amplification type input buffer shown in
FIG. 3
, transconductance gain gm decreases slightly when a reference voltage VREF decreases. Accordingly, low voltage interface characteristics deteriorate, and the operating speed of the input buffer decreases.
SUMMARY OF THE INVENTION
To solve the above problem, an embodiment of the present invention provides an input buffer circuit that supports both a low voltage interface and a low voltage transistor-transistor logic (LVTTL) interface and operates at high speed.
One particular embodiment of the invention is an input buffer circuit including a differential amplification circuit, a current controlling circuit, and a swing width control circuit. The differential amplification circuit generates an internal self bias signal and an output signal, based on a voltage difference between a reference voltage and an input signal. The current controlling circuit responds to the internal self bias signal, supplies current to the differential amplification circuit, and sinks current from the differential amplification circuit to maintain the internal self bias signal at substantially uniform level. The swing width control circuit responds to an inverted signal generated from the output signal and limits the voltage swing of the output signal.
The swing width control circuit preferably includes an NMOS transistor and a PMOS transistor. The NMOS transistor is between an output node of the differential amplification circuit, from which the output signal is output, and a first node of the current control circuit. The NMOS transistor responds to the inverted signal. The PMOS transistor is between the output node of the differential amplification circuit and a second node of the current control circuit. The PMOS transistor also responds to the inverted signal.
The current control circuit preferably comprises a current source and/or a current sink. The current source is between a supply voltage terminal and the differential amplification circuit and supplies current to the differential amplification circuit in response to the internal self bias signal. The current sink is between the differential amplification circuit and a ground voltage terminal and sinks current from the differential amplification circuit in response to the internal self bias signal. Preferably, the current source is a PMOS transistor, and the current sink is an NMOS transistor.
According to an exemplary embodiment, the differential amplification circuit includes a self biased differential amplifier including first through fourth PMOS transistors and first through fourth NMOS transistors. The first PMOS transistor is between the first node of the current control circuit and an internal node from which the internal self bias signal is output and is gated by the reference voltage. The second PMOS transistor is between the first node and the internal node and is gated by the internal self bias signal. The third PMOS transistor is between the first node and an output node from which the output signal is output and is gated by the internal self bias signal. The fourth PMOS transistor is between the first node and the output node and is gated by the input signal. The first NMOS transistor is between the second node of the current control circuit and the internal node and is gated by the reference voltage. The second NMOS transistor is between the second node and the internal node and is gated by the internal self bias signal. The third NMOS transistor is between the second node and the output node and is gated by the internal self bias signal. The fourth NMOS transistor is between the second node and the output node and is gated by the input signal.
According to another embodiment, the differential amplification circuit includes a self biased latch type differential amplifier, which include a positive feedback loop in the form of a latch. More particularly, the self biased latch type differential amplifier include first through fifth PMOS transistors and first through fifth NMOS transistors. The first PMOS transistor is between the first node of the current control circuit and an internal node from which the internal self bias signal is output and is gated by the reference voltage. The second PMOS transistor is between the first node and the internal node and is gated by the output signal. The third PMOS transistor is gated by the internal self bias signal and is between the first node and an output node from which the output signal is output. The fourth PMOS transistor is between the first node and the output node and is gated by the input signal. The fifth PMOS transistor has a source connected to the first node and a gate and a drain commonly connected to the internal node. The first NMOS transistor is between the second node of the current control circuit and the internal node and is gated by the reference voltage. The second NMOS transistor is between the second node and the internal node and is gated by the output signal. The third NMOS transistor is between the second node and the output node and is gated by the internal self bias signal. The fourth NMOS transistor is between the second node and the output node and is gated by the input signal. The fifth NMOS transistor has a gate and a drain commonly connected to the internal node and a source connected to the second node.


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