High speed I.sub.DDQ monitor circuit

Details High speed I.sub.DDQ monitor circuit High speed I.sub.DDQ monitor circuit

1995-06-05

1996-09-03

Nelms, David C.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Delay controlled switch

327403, 327404, H03K 1728, H03K 1762

Patent

active

055527442

ABSTRACT:
A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

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