High-speed high-density SRAM cell

Details High-speed high-density SRAM cell High-speed high-density SRAM cell

1994-10-20

1996-05-28

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365154, 257903, G11C 1100

Patent

active

055218610

ABSTRACT:
A six-transistor SRAM of a high-density memory comprises two thin-film n-channel pull-down transistors and four conventional p-channel load and access transistors. As embodied in a semiconductor chip, the cell is simpler than priorly known six-transistor cells and is relatively immune from the deleterious effects of sodium ions and hot-carrier aging.

REFERENCES:
patent: 4623989 (1986-11-01), Blake
patent: 5327377 (1994-07-01), Kawashima
patent: 5404326 (1995-04-01), Okamoto
H. J. M. Veendrick, MOS ICs, 1992, pp. 310-311, VCH Publishers Inc., New York.
C. T. Liu et al, High Reliability & High Performance . . . Using Seif-Aligned LDD Structures, 1992, pp. 823-826, IEDM 92.

Affiliated with

Also associated with

Rating

High-speed high-density SRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-speed high-density SRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed high-density SRAM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-792413