High speed global row redundancy system

Details High speed global row redundancy system High speed global row redundancy system

1994-09-29

1996-06-18

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Bad bit

371 102, 371 103, 3652257, 36523003, 36523006, G11C 700, G11C 2900

Patent

active

055285392

ABSTRACT:
A row repair system for replacing a defective primary memory row with a redundant memory row within an entire section of an integrated circuit memory chip. The system comprises a dedicated match circuit for each redundant row in a given section. The match circuit analyzes incoming address information to determine whether the address corresponds to a memory location in a specific defective row in any one of a number of sub-array blocks within the section. When such a critical address is detected, the match circuit activates circuitry which inhibits access to the defective row and enables access to its dedicated redundant row.

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Journal of IEEE International Solid State Circuit Conference 1990, pp. 232-233 and 303 Kalter et al.

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