High speed floating point type multiplier circuit

Details High speed floating point type multiplier circuit High speed floating point type multiplier circuit

1990-11-21

1992-09-01

Nguyen, Long T.

Boots, shoes, and leggings

G06F 738

Patent

active

051445751

ABSTRACT:
A floating point multiplier circuit for multiplying two binary numbers includes a multiplier, a binary point processing device, a first network adder/subtracter, a second adder/subtracter, and a control device. In the floating point multiplier circuit, the circuit for operating the exponent and mantissa is designed using a parallel arrangement of PMOS and NMOS transistors. Faster operation is realized by transmitting in parallel a given input and a resulting output. Furthermore, the structure is much simpler than configurations using conventional logic gates thereby resulting in reduced chip area and efficient use of VLSI design methodologies.

REFERENCES:
patent: 4941122 (1990-07-01), Weideman

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