High speed flip-flops and complex gates using the same

Details High speed flip-flops and complex gates using the same High speed flip-flops and complex gates using the same

2007-10-29

2009-02-17

Lam, Tuan T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S203000, C326S095000

Reexamination Certificate

active

07492203

ABSTRACT:
In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.

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