High speed flip-flop for gate array

Details High speed flip-flop for gate array High speed flip-flop for gate array

1994-11-29

1997-03-18

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

327203, 326 93, H03K 19173, H03K 1900

Patent

active

056126328

ABSTRACT:
A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.

REFERENCES:
patent: 5105100 (1992-04-01), Yamada
patent: 5107137 (1992-04-01), Kinugasa et al.
patent: 5173626 (1992-12-01), Kudou et al.
patent: 5317205 (1994-05-01), Sato

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