High speed flexible slave interface for parallel common bus to l

Details High speed flexible slave interface for parallel common bus to l High speed flexible slave interface for parallel common bus to l

1996-02-28

1998-06-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

364DIG1, 3642434, 36424345, 3642318, 711135, 711141, 711142, G06F 1200, G06F 1300

Patent

active

057617074

ABSTRACT:
An interface for transferring data via a PCI bus between a initiator device and a host target having a local cache buffer. The PCI interface to the local cache buffer includes an interface controller, an address resolution unit, data and address logic, byte enable logic and command processing logic. The command and data logics resolve address hits and misses and determine when a write operation will occur to the local cache buffer. The interface controller performs hand shaking operations between the PCI interface and an initiator device connected via the PCI bus. The interface controller also regulates the transfer of data between the device initiator and the local cache buffer, providing status and control signals to the cache controller during a given transfer cycle. The data logic receives the data from the PCI bus and verifies parity providing data and parity information to the cache buffer and cache parity error buffer. The byte enable logic receives and processes byte enable information associated with each data transfer phase and generates start pointer and end pointer information for a determination of the valid data bytes which are stored in a particular cache line. Finally, the interface controller generates an end of line signal upon the completion of a cache line write allowing for the transfer of uniform data blocks across the cache buffer to host boundary.

REFERENCES:
patent: 5479641 (1995-12-01), Nadir et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5581727 (1996-12-01), Collins et al.

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