Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-02-04
1998-06-02
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257318, 257321, 257324, H01L 29788
Patent
active
057604380
ABSTRACT:
A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor. During programming, coupling is improved at the gate of the programming transistor by an erase node boosting technique. This technique involves applying a relatively "boosted" voltage level to the drain region of the erase node which reduces the backbias threshold effect of erase node capacitors. Similarly, during a read operation, a relatively "boosted" voltage is applied to the drain region of the erase node, which, by way of the buried implant plate, reduces the backbias threshold effect of the erase node capacitors wherein coupling at the control gate of the read transistor is improved.
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Hu Genda J.
Norris Christopher S.
Sethi Rakesh Balraj
Cypress Semiconductor Corporation
Ngo Ngan V.
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