High speed FIFO synchronous programmable full and empty flag...

Details High speed FIFO synchronous programmable full and empty flag... High speed FIFO synchronous programmable full and empty flag...

2006-10-03

2006-10-03

Browne, Lynne H. (Department: 2116)

Static information storage and retrieval

Read/write circuit

Serial read/write

Reexamination Certificate

active

07116599

ABSTRACT:
An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.

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patent: 5627797 (1997-05-01), Hawkins et al.
patent: 6347380 (2002-02-01), Chang et al.
Johnie Au et al., “A High Speed Synchronous and Programmable State Machine for Generating Almost Empty Synchronous Flags in a Synchronous FIFO”, U.S. Appl. No. 09/895,305, filed Jun. 30, 2001.
Johnie Au et al., “A High Speed Synchronous and Programmable State Machine for Generating Almost Empty Synchronous Flags in a Synchronous FIFO”, U.S. Appl. No. 09/895,306, filed Jun. 30, 2001.
Johnie Au et al., “High Speed FIFO Synchronous Programmable Full and Empty Generation”, U.S. Appl. No. 09/957,015, filed Sep. 20, 2001.

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