High speed FIFO synchronous programmable full and empty flag...

Details High speed FIFO synchronous programmable full and empty flag... High speed FIFO synchronous programmable full and empty flag...

2001-09-20

2003-02-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189011

Reexamination Certificate

active

06525980

ABSTRACT:

FILED OF THE INVENTION
The present invention relates to a method and/or architecture for generating flags in a memory generally and, more particularly, to a method and/or architecture for generating high speed almost empty status flags in a first-in, first-out (FIFO) memory.
BACKGROUND OF THE INVENTION
First-in first-out (FIFO) memories provide a temporary buffer (or storage area) between communication systems. A programmable empty flag of a FIFO can be used as an interrupt to warn the system when the FIFO buffer becomes almost empty, which then blocks further read operations. Almost empty flags are generated in real-time to prevent underflow of the buffer. Traditionally, read counters, write counters and an offset register are used to track the status of the FIFO.
Referring to
FIG. 1
, an almost empty flag generation circuit
10
implementing a 3-input adder is shown. The circuit
10
includes a write counter
12
, a read counter
14
, a program value (i.e., an offset register)
16
, a 3-input carry look ahead adder/comparator
18
, an adder glitch filter
20
and a programmable almost empty flag register
22
. The circuit
10
receives a FIFO write clock WRCLK and a FIFO read clock RDCLK. The write counter
12
presents a value to the adder/comprator circuit
18
in response to the FIFO write clock WRCLK. The write counter
12
tracks the number of writes. The read counter
14
presents a value to the adder/comparator circuit
18
in response to the FIFO read clock RDCLK. The read counter
14
tracks the number of reads. The offset register
16
stores a user programmed offset value. The adder/comparator circuit
18
also receives the offset value from the register
16
. The adder/comparator
18
presents an output to the programmable almost empty register
22
via the adder glitch filter
20
. The glitch filter
20
degrades performance of the circuit
10
(i.e., the glitch filter
20
is slow). The programmable almost empty register
22
then presents the full status flag EMPTY. The almost empty status flag EMPTY is obtained by the 3-input adder
18
which is in the critical path. The 3-input adder is slow and restricts the operational speed of the circuit
10
.
Conventional almost empty flags that use a 3-input adder define the almost empty flag as EMPTY=(WR−RD<(offset)). Such an approach may have one or more of the following disadvantages of (i) being slow, (ii) consuming large area, and/or (iii) having wide glitches generated by the adder which need filtering, thereby degrading overall performance.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a flag generation circuit configured to generate an empty flag signal in response to (i) a read clock, (ii) a write clock and (iii) a look ahead bitwise comparison configured to detect when a write count signal minus a read count signal is equal to 1.
The objects, features and advantages of the present invention include providing a method and/or architecture for generating high speed almost empty status flags in a FIFO that may (i) use a comparator to generate look ahead signals used by the almost empty flag generation, (ii) use state machines (e.g., asynchronous state machines) to generate the almost empty flag, (iii) implement a user programmable offset directly into the read counter upon programming, (iv) implement a shadow register for storing the offset value, (v) achieve high speed operation (e.g., 266 MHz) and/or (vi) minimize logic hazards (e.g., glitches).


REFERENCES:
patent: 5278956 (1994-01-01), Thomsen et al.
patent: 5406554 (1995-04-01), Parry
patent: 5517627 (1996-05-01), Petersen
patent: 6070203 (2000-05-01), Hawkins et al.
Johnie Au et al., “High Speed Asynchronous and Programmable State Machine for Generating Almost Empty Synchronous Flags in a Synchronous FIFO”, U.S. Serial No. 09/895,305, Filed Jun. 30, 2001.
Johnie Au et al., “High Speed Asynchronous and Programmable State Machine for Generating Almost Empty Synchronous Flags in a Synchronous FIFO”, U.S. Serial No. 09/895,306, Filed Jun. 30, 2001.
Johnie Au et al., “High Speed FIFO Synchronous Programmable Full and Empty Generation”, U.S. Serial No. 09/957,587, Filed Sep. 20, 2001.

Affiliated with

Also associated with

Rating

High speed FIFO synchronous programmable full and empty flag... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed FIFO synchronous programmable full and empty flag..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed FIFO synchronous programmable full and empty flag... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3123698