High speed FIFO mark and retransmit scheme using latches and pre

Details High speed FIFO mark and retransmit scheme using latches and pre High speed FIFO mark and retransmit scheme using latches and pre

1996-12-18

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

36518912, G06F 1200

Patent

active

058601600

ABSTRACT:
The present invention provides a look ahead architecture to satisfy the retransmit recovery time constraints in a mark and retransmit system while allowing a full bitline precharge. A number of sense amplifiers are provided in the look ahead architecture that may be equipped with a "shadow latch" to store the read data when the mark pointer is asserted. As a result, the data to be retransmitted will be retrieved from the shadow latches when the retransmit is asserted, allowing a full precharge cycle before reading from the memory array.

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