High speed encoder and method thereof

Details High speed encoder and method thereof High speed encoder and method thereof

2000-12-08

2002-08-27

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06441768

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an encoder, and more particularly, to an encoder which operates at high speed and uses a small amount of power, and an encoding method using the same.
2. Description of the Related Art
In conventional flash-type analog-to-digital converters (hereinafter, referred to as ADCs), the outputs of comparators form a thermal code. Here, an encoder converts the thermal code into a binary code or a binary-coded-decimal (BCD) code to perform further processing on the thermal code. The encoder must operate at high speed and provide a high resolution in communications systems where an analog video signal or an analog audio signal is converted into a digital signal. Existing types of encoders include a priority encoder and a memory cell encoder.
FIG. 1
is a block diagram of a conventional priority encoder. The priority encoder of
FIG. 1
converts 16-bits produced from an analog signal into 4 bits, which correspond to least significant bits (LSBs), and 2 bits, which correspond to most significant bits (MSBs).
Referring to
FIG. 1
, a code generator
110
converts an analog signal of 64 levels into a digital signal of 16 bits (b
0
-b
15
). An LSB encoder
100
is made up of first, second, third, fourth and fifth encoders
111
,
112
,
113
,
114
and
115
and first and second selectors
116
and
117
. That is, the first, second, third and fourth encoders
111
,
112
,
113
and
114
receive b
0
through b
3
, b
4
through b
7
, b
8
through b
11
and b
12
through b
15
, respectively, and encode the received four bits into 3-bits. The fifth encoder
115
receives four bits, one from each of the first, second, third and fourth encoders
111
,
112
,
113
and
114
, and encodes the four bits into two LSBs b
2
and b
3
. Further, each of the first and second selectors
116
and
117
encodes 4 bits, which are output from each of the first, second, third and fourth encoders
111
,
112
,
113
and
114
, into bits b
1
and b
0
, respectively.
An MSB encoder
122
encodes four MSBs B
0
through B
3
into two MSBs B
0
and B
1
. A corrector
120
corrects six received bits b
0
through b
3
and B
0
and B
1
.
The priority encoder as shown in
FIG. 1
performs all operations using a signal output from an ADC, so that a large capacity buffer is needed, and the critical path becomes long. The large-capacity buffer and the long critical path of the priority encoder of
FIG. 1
cause high power consumption and a long delay in the processing of digital signals. Also, the priority encoder as shown in
FIG. 1
includes selectors
116
and
117
and has a complicated circuit structure, so that it is disadvantageous in terms of speed and power.
Memory cell type encoders are also enlarged with an increase in the number of input bits, and a complicated data path causes delay and noise.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a high-speed encoder in which the current consumption and delay time are reduced by shortening a data path without increasing the area of use.
Another objective of the present invention is to provide an encoding method for reducing current consumption and delay time by shortening a data path without increasing the area of use.
To achieve the first objective, the present invention provides a high-speed encoder including: a switching unit for receiving a thermal code of a predetermined number of bits received in series, and outputting one bit among the received bits as a most significant bit and the other bits in parallel; and an encoder for dividing the bits received from the switching unit in parallel into groups having a predetermined number of bits, encoding the bits in each group into a predetermined number of bits, selecting one group of encoded bits using bits not used by the groups, and outputting least significant bits together with the most significant bit output from the switching unit. The encoder includes: a block unit for dividing the received bits into blocks having a predetermined number of bits and encoding the signals in each group into a predetermined number of bits; a selection unit for selecting the encoded bits in one among the blocks by combining bits not used by the blocks among the received bits; and a bit generation unit for generating bits other than the encoded bits selected by the selection unit and the bit generated by the switching unit, by combining the unused bits.
To achieve the second objective, the present invention provides a method of encoding a thermal code output from an analog-to-digital converter, the method including: dividing received bits into blocks having a predetermined number of bits and encoding the bits in each group into a predetermined number of bits; selecting one among the blocks by combining bits not used by the blocks among the received bits, and generating the encoded bits in the selected block; and generating bits other than the encoded bits generated in the previous step, by combining the unused bits.


REFERENCES:
patent: 4586025 (1986-04-01), Knierim
patent: 5155489 (1992-10-01), Gulczynski
patent: 5243348 (1993-09-01), Jackson
patent: 5252974 (1993-10-01), Gulczynski
patent: 5382955 (1995-01-01), Knierim

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