High speed embedded DRAM with SRAM-like interface

Details High speed embedded DRAM with SRAM-like interface High speed embedded DRAM with SRAM-like interface

2005-09-06

2005-09-06

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S118000, C711S154000

Reexamination Certificate

active

06941414

ABSTRACT:
The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.

REFERENCES:
patent: 6157973 (2000-12-01), Ohtani et al.
patent: 6295593 (2001-09-01), Hsu et al.
patent: 6347063 (2002-02-01), Dosaka
patent: 6415353 (2002-07-01), Leung
Yasuharu Sato, et al., “Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipe-Lined Operating DRAM”,IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 22-25, Jun. 1998.
Yasuhiro Agata, et al., An 8ns Random Cycle Embedded RAM Macro with Dual-Port Interleaved DRAM Architecture (D2RAM),IEEE International Solid-State Circuits Conference, pp. 392-393, Feb. 9, 2000.

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