Static information storage and retrieval – Read/write circuit
Patent
1990-06-29
1993-02-09
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
365203, 365193, 36523001, G11C 1300
Patent
active
051857197
ABSTRACT:
A computer system is described which includes a DRAM having a plurality of memory cells arranged in rows and columns. The system includes a row address buffer, and circuitry for generating a row address strobe signal that exhibits both active and inactive levels during each DRAM memory cycle and first and second transitions between those levels. A read-in circuit causes read-in of a row address to the DRAM's row address buffer. A delay circuit is responsive to a delayed lagging transition of a row address strobe signal to provide an extended duration control signal which delays an output from the row address buffer. A reset/precharge circuit is active during both the inactive row address strobe signal and the extended duration control signal to reset and precharge circuits and memory cells in the DRAM.
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Dhong Sang H.
Hwang Wei
Fears Terrell W.
International Business Machines Corp.
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