High speed DRAM local bit line sense amplifier

Details High speed DRAM local bit line sense amplifier High speed DRAM local bit line sense amplifier

2001-02-07

2002-07-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

C365S203000, C365S208000, C365S210130

Reexamination Certificate

active

06426905

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention generally relates to DRAMs; and more specifically, to sense amplifiers (or sense “amps”) used in DRAMS.
Today'S DRAM technology tends to provide a high density of electronic memory, but with relatively slow random (row) access time. This is primarily due to the industry's efforts at growing the density of DRAM chips by 4× every generation (every 3 years). Bit lines are made very long and heavily loaded. Bit line sensing has been done with standard latch-type sense amps using a folded differential bit line approach and several on-chip generated clocks for latching the data in the sense amp. Typical row access times have been about 30-40 ns at chip level, which has been adequate for most main memory applications.
With today's interest in merging DRAM and logic technology on the same chip, there is an interest in building DRAM macros of about 1 Mbits or 2 Mbits each and merging these within the logic of the particular chip, depending upon the application.
SUMMARY OF THE INVENTION
An object of this invention is to provide very high speed DRAM macros that have the cell density of DRAM single transistor cells with the access time and cycle time speeds more typical of SRAM technology.
Another object of the present invention is to provide for very high speed local bit line sensing which can be used to set a macro output latch/driver for a very high bandwidth and low latency memory.
A further object of this invention is to provide a 1 M bit DRAM macro that can be accessed (random access) in about 5 ns nominal delay using CMOS technology with embedded DRAM.
These and other objectives are attained with a sense amplifier for detecting a change of charge out of an input node, and comprising a first current source and a first field effect transistor. The current source is provided for removing charge from the input node. The field effect transistor includes (i) a source coupled to the input node, (ii) a gate electrode coupled to a first voltage, and (iii) a drain coupled to one side of a first capacitor, to an output node, and to a precharge circuit for setting the voltage of the output node to a second voltage, providing a voltage difference between the drain and source of said first transistor. The other side of the capacitor is coupled to ground.
With a preferred embodiment, the precharge circuit includes a control signal coupled to a gate of a second field effect transistor for turning off the precharge circuit prior to sensing, and the sense amplifier further includes a second current source coupled to the output node for supplying charge to the output node. Also, the charge removed by the first current source is preferably substantially equal to the charge added by the second current source. The first current source is preferably set to bias the first field effect transistor to conduct at a current corresponding to the current at weak inversion (near the threshold voltage) of the first field effect transistor.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.


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