High speed DRAM cache architecture

Details High speed DRAM cache architecture High speed DRAM cache architecture

2006-01-10

2008-03-25

Song, Jasmine (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S128000, C711S202000, C711S211000, C365S049130, C365S230010, C365S230020, C365S230030

Reexamination Certificate

active

07350016

ABSTRACT:
A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

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