High-speed discharge-suppressed D flip-flop

Details High-speed discharge-suppressed D flip-flop High-speed discharge-suppressed D flip-flop

2002-08-26

2004-01-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S210000

Reexamination Certificate

active

06680638

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-59041, filed on Sep. 24, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to semiconductor integrated circuits. More particularly, the invention relates to a D flip-flop that is synchronized with a clock signal to have a memory function for storing an input signal or for outputting the stored signal.
BACKGROUND OF THE INVENTION
In recent years, the development of information and communication technologies has had a great effect on society and culture. Particularly, the rapid advancement of the Internet technologies, personal terminals, and portable computers requires processing of a large amount of information. This has driven toward the successful development of microprocessors having a clock speed of greater than 1 GHz.
In view of the trend toward high integration and high speed systems, internal circuits constituting a high-speed digital system or a clock network must be carefully designed. The internal circuits of the high-speed digital system have at least two functions. The first is a logic function for transmitting a desired output signal in response to an input signal, and the second is a memory function for storing an input signal or outputting the stored signal in synchronization with a clock signal. Flip-flops are essential components in both functions, but especially in a circuit block having the memory function.
The most basic structure of the flip-flop is a master-slave structure having two JK latches that are coupled. However, this structure cannot be applied to a high-speed digital system because of its complexity and low operation speed. In order to overcome these disadvantages of the master-slave structure, dynamic type flip-flops using a parasitic capacitance of an internal node have been developed. Unfortunately, the dynamic type flip-flop requires two or more clock signals and is very sensitive to a racing problem generated by skew between the clock signals. In order to overcome these disadvantages of the dynamic type flip-flop, true single phase clocking (TSPC) D flip-flips have been proposed. The TSPC D flip-flop uses only one clock signal that is not absolutely inverted, and offers advantages such as a small area for clock lines, a reduced clock skew, and high speed operation. One example of the TSPC D flip-flop is disclosed in U.S. Pat. No. 6,060,927 entitled “HIGH-SPEED D FLIP-FLOP”, the content of which is incorporated herein by reference, in their entirety.
FIG. 1A
is a circuit diagram of the TSPC D flip-flop illustrated in U.S. Pat. No. 6,060,927 and shows a technology to achieve a low power consumption and a high-speed response caused by an internal capacitance reduction. A flip-flop shown in
FIG. 1A
includes first to third latches. The first latch receives a clock signal CLK and a data signal D to generate a first output signal Q
1
′. The second latch receives the first output signal Q
1
′ and the clock signal CLK to generate a second output signal Q
1
″. The third latch receives the second output signal Q
1
″ and the clock signal CLK to generate a third output signal/Q
1
. The inverter
17
receives the third output signal/Q
1
to generate a data signal Q
1
at a rising or falling edge of the clock signal CLK. Preferably, the first and second latches are ratioed latches having serially coupled pull-up and pull-down elements. Preferably, the third latch is a clock operated latch.
Since static current always flows to the ratioed latch, the ratioed latch consumes a considerable amount of current. Also, since the voltage at each connecting node of the pull-up and pull-down elements does not fully swing, the ratioed latch is very sensitive to noise. Therefore, it is very difficult to design the ratioed latch. That is, in the ratioed latch, the pull-up elements must be designed to be 7-8 times larger than the pull-down elements.
Another example of the TSPC D flip-flop is disclosed in U.S. Pat. No. 5,592,114 entitled “TRUE TYPE SINGLE-PHASE SHIFT CIRCUIT”, the content of which is incorporated herein by reference, in its entirety.
FIG. 1B
is a circuit diagram of the TSPC D flip-flop illustrated in the U.S. Pat. No. 5,592,114. A TSPC D flip-flop shown in
FIG. 1B
is a positive edge-triggered D flip-flop including four PMOS transistors MP
0
, MP
1
, MP
2
, and MP
3
, and five NMOS transistors MN
0
, MN
1
, MN
2
, MN
3
, and MN
4
. A gate of the PMOS transistor MP
0
and a gate of the NMOS transistor MN
0
are connected to a data signal D. Gates of the PMOS transistors MP
1
and MP
2
and gates of the NMOS transistors MN
2
and MN
3
are connected to a clock signal CLK. A drain of the PMOS transistor MP
3
and a drain of the NMOS transistor MN
3
are connected to an output terminal Qb. A gate of the NMOS transistor MN
1
is connected to an A node, i.e., a common drain node A to which a drain of the PMOS transistor MN
1
and a drain of the NMOS transistor MN
0
are commonly connected. A gate of the PMOS transistor MP
3
and a gate of the NMOS transistor MN
4
are connected to a B node, i.e., a common drain node B to which a drain of he PMOS transistor MP
2
and a drain of the NMOS transistor MN
1
are commonly connected.
When the clock signal CLK is low (e.g., ground voltage) and a data signal D is low, the potential of the A node is made low or high (e.g., power supply voltage Vcc) according to the data signal D. Meanwhile, when the clock signal CLK is low and the data signal D is high, the potential of the A node is made low. In this case, the B node is precharged to a high level. When the B node is precharged, an output terminal Qb is to latch a previous output value. Therefore, the B node maintains the previous output value. When the clock signal CLK has a low-to-high transition, a potential of the B node is to be held at a previously precharged level or is to be made low. Therefore, a potential of the output terminal Qb is to be made low or high.
Limitations of the TSPC D flip-flop shown in
FIG. 1B
will now be described. The first limitation is that the flip-flop is very sensitive to a clock slope (rising or falling time of a clock signal). This will be explained in detail below.
FIG. 2
shows output waveforms obtained when a clock slope is maintained at 0.3 ns in a clock frequency of 100 MHz. In
FIG. 2
, the region of the output terminal signal Qb enclosed in a dashed circle is ideally a period that must be maintained high. Nonetheless, the voltage level of the output terminal Qb is unstably maintained during this period.
This unstable period arises because the moment the data signal D is low and the clock signal CLK transitions high to low, charges of the output terminal Qb are discharged. That is, if the slope of the clock signal CLK is not quite vertical, there is a period where the NMOS transistors MN
3
and MN
4
are transitorily turned on at the same time. This allows the charges of the output terminal Qb to be discharged through the NMOS transistors MN
3
and MN
4
. More specifically, when the potential of the B node transitions low to high and the clock signal transitions high to low, there is a period where the high levels overlap each other, as shown in FIG.
3
. This allows the NMOS transistors MN
3
and MN
4
to be turned on at the same time. Consequently, the charges of the output terminal Qb are discharged through the turned-on transistors MN
3
and MN
4
. The gentler the clock slope becomes, the more the overlap periods of the high level increase. In a worst case scenario, erroneous data may be transmitted. As a result, the TSPC D flip-flop shown in
FIG. 1B
is very sensitive to the clock slope.
A second limitation associated with the TSPC D flip-flop shown in
FIG. 1B
is that a glitch can occur. Whenever the data signal D is maintained low and the clock signal CLK transitions low to high, the glitch occurs in the output signal Qb, as illustrated in the region enclosed by the dotted line in FIG.
4
. Ideally,

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