Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-11-19
1999-03-23
Pham, Chi H.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327152, H04L 700
Patent
active
058870407
ABSTRACT:
The present invention provides a high speed digital data retiming apparatus, in which, in binary data bits transmitted at a high speed, the data can be retimed in a stable manner, even if there are present a static skew due to a delay difference between the retiming clock pulse and the data and a dynamic skew due to the characteristic variation according to time and temperature. Therefore, the present invention has the following advantages compared with the conventional apparatus. First, periodical and regular external clock pulses are delayed by means of a delaying section, so that system performance is independent of the pattern of data. Second, even if the data phases show a continuous difference (wandering) for more than a certain period of time, an elastic buffer absorbs the wandering, and therefore, no data loss is generated, with the result that the system is not put to a disorder condition. Third, even in the case where a metastable state occurs, its occurrence probability can be significantly reduced by utilizing logic, thereby making it possible to retime the data in stable manner.
REFERENCES:
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A 45-Mbit/s CMOS VLSI Digital Phase Aligner; Robert R. Cordell; 1988; pp. 323-328.
Jung Hee-Young
Lee Bhum-Cheol
Park Kwon-Chul
Electronics and Telecommunications Research Institute
Korea Telecommunication Authority
Luther William
Pham Chi H.
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