High speed differential to single ended sense amplifier

Static information storage and retrieval – Read/write circuit – Differential sensing

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365208, 327 51, 327 52, 327 53, G11C 702

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055770010

ABSTRACT:
A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

REFERENCES:
patent: 4475178 (1984-10-01), Kinoshita
patent: 4654831 (1987-03-01), Venkatesh
patent: 4725984 (1988-02-01), Ip et al.
patent: 4802138 (1989-01-01), Shimamune
patent: 4829479 (1989-05-01), Mitsumoto
patent: 4903237 (1990-02-01), Rao
patent: 4903238 (1990-02-01), Miyatake et al.
patent: 4918341 (1990-04-01), Galbraith et al.
patent: 4935649 (1990-06-01), Bloker
patent: 5013943 (1991-05-01), Hirose
patent: 5117394 (1992-05-01), Amin et al.
patent: 5202854 (1993-04-01), Koike
patent: 5227697 (1993-07-01), Sakagami
patent: 5237533 (1993-08-01), Papaliolios
patent: 5255230 (1993-10-01), Chan et al.
patent: 5305259 (1994-04-01), Kim
patent: 5355343 (1994-10-01), Shu et al.
patent: 5357468 (1994-10-01), Satani et al.
A 25-ns 16K CMOS PROM Using a Four-Transistor Cell and Differential Design Techniques, Pathak et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985.
A 25-ns 16K CMOS PROM Using a 4-Transistor Cell, Pathak et al., IEEE Intl. Solid-State Circuits Conference, Feb. 1985.
A Fault-Tolerant 30 ns/375 mW 16Kx1 NMOS Static RAM, Hardee et al., IEEE Journal of Solid State Circuits, vol. SC-16, No. 5, Oct. 1981.
The Technology of a 1Mbit CMOS EPROM, by Guy Nelmes, New Electronics, vol. 18, No. 22.
A 1Mb CMOS EPROM with Enhanced Verification, 1988 IEEE Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1988.
Principles of CMOS VLSI Design, A Systems Perspective, Weste et al., pp. 362-364, Jun. 1988.

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